CSR60: Previous Transmit Descriptor Address
Lower
CSR63: Previous Transmit Status
Bit
Name
Description
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0 PXST
Previous Transmit Status. This
field is a copy of bits 31-16 of
TMD1 of the previous transmit
descriptor.
15-0 PXDAL
Contains the lower 16 bits of the
previous transmit descriptor ad-
dress pointer. The Am79C978
controller has the capability to
stack multiple transmit frames.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR64: Next Transmit Buffer Address Lower
Bit
Name
Description
CSR61: Previous Transmit Descriptor Address
Upper
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
Bit
Name
Description
15-0 NXBAL
Contains the lower 16 bits of the
next transmit buffer address from
which the Am79C978 controller
will transmit an outgoing frame.
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0 PXDAU
Contains the upper 16 bits of the
previous transmit descriptor ad-
dress pointer. The Am79C978
controller has the capability to
stack multiple transmit frames.
These bits are read/write accessi-
ble only when either the STOP or
the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR65: Next Transmit Buffer Address Upper
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
CSR62: Previous Transmit Byte Count
Bit
Name
Description
15-0 NXBAU
Contains the upper 16 bits of the
next transmit buffer address from
which the Am79C978 controller
will transmit an outgoing frame.
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-12 RES
Reserved locations.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
11-0 PXBC
Previous Transmit Byte Count.
This field is a copy of the BCNT
field of TMD1 of the previous
transmit descriptor.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
136
Am79C978
AMD [ AMD ]
