AMD
P R E L I M I N A R Y
Test Conditions
PCMCIA I/O WRITE ACCESS
Parameter
Symbol
Parameter Description
Address setup to IOWR ↓
Address hold from IOWR ↑
REG setup to IOWR ↓
REG hold from IOWR ↑
CE setup to IOWR ↓
CE hold from IOWR ↑
IOWR width
Min
70
20
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVIWL
tIWHAX
tRGLIWL
tIWHRGH
tELIWL
0
5
tIWHEH
20
165
tIWLIWH
tIWLWTL
tWTLWTH
tWTHIWH
tDVIWL
WAIT ↓ delay from IOWR ↓
WAIT width
35
Notes 1, 2
53 X TCLKIN
IOWR ↑ from WAIT ↑
Data setup to IOWR ↓
Data hold from IOWR ↑
0
60
30
tIWHDX
Notes:
1. The max value for this parameter assumes the following worst case situation:
Value
Worst Case
0
1
FLASH and SRAM wait states set at “3.”
Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins
instruction fetch cycle to FLASH memory.
2
PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188
controller access.
3
4
Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle.
After completion of first embedded 80188 access to FLASH, posted PCMCIA WRITE executes to SRAM;
PCMCIISA READ stycle is being held in wait state.
5
6
After completion of posted PCMCIA WRITE cycle, new embedded 80188 access to FLASH begins.
After completion of second embedded 80188 access to FLASH, PCMCIA READ cycle is allowed to proceed onto
memory bus to SRAM; host is still held in wait state.
7
At SRAM READ cycle completion, data is delivered to PCMCIA bus and wait state is exited.
2. Parameter is not included in production test.
134
Am79C930
AMD [ AMD ]
