AMD
P R E L I M I N A R Y
Test Conditions
ISA ACCESS
Parameter
Symbol
Parameter Description
Min
60
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ti1
ti2
LA[23:17] valid setup to BALE ↓
BALE ↑ to BALE ↓ pulse width
LA[23:17] valid hold from BALE ↓
LA[23:17] valid setup to CMD ↓
SA[16:0] valid setup to CMD ↓
CMD ↓ to CMD ↑ pulse width
SA[16:0] valid setup to BALE ↓
Data valid delay from RCMD ↓
Data valid setup to WCMD ↓
SA[16:0] valid hold from CMD ↑
CMD ↑ to CMD ↓ pulse width
Data valid hold from RCMD ↑
Data valid hold from WCMD ↑
Data disabled from RCMD ↑
IOCHRDY ↓ delay from CMD ↓
25
ti3
12
ti4
Note 1
Note 1
Note 4
80
ti7
25
ti8
6*TCLKIN
20
ti9
ti10
ti11
ti12
ti13
ti14
ti15
ti16
ti20
ti21
Notes 2, 5, 6
Note 3
53 X TCLKIN
–75
20
55
0
Note 1
Note 1
Note 2
Note 3
20
Note 2, 6
Notes 1, 7
Notes 5, 6, 7
20
60
IOCHRDY ↓ to IOCHRDY ↑
0
130 +
pulse width
53 X TCLKIN
ti22
ti23
ti25
ti26
ti30
ti31
ti32
ti34
CMD ↑ delay from IOCHRDY ↑
BALE ↑ delay from CMD ↑
Notes 1, 7
Note 1
35
20
ns
ns
ns
ns
ns
ns
ns
ns
Data valid delay from IOCHRDY ↑ Note 7
–TCLKIN
–15
80
25
LA[23:17] valid hold from CMD ↓
AEN valid setup to CMD ↓
AEN valid hold from CMD ↑
AEN valid setup to BALE ↓
Data enabled from RCMD ↓
Note 1
Note 1
Note 1
15
60
Notes 2, 4
0
110
Notes:
1. CMD = one of: MEMR, MEMW, IOR or IOW.
2. RCMD = one of: MEMR, or IOR.
3. WCMD = one of: MEMW, or IOW.
4. If no wait states are incurred.
5. The max value for this parameter assumes the following worst case situation:
Value
Worst Case
0
1
FLASH and SRAM wait states set at “3.”
Host performs ISA WRITE cycle at same time that Am79C930 embedded 80188 controller begins
instruction fetch cycle to FLASH memory.
2
ISA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188
controller access.
3
4
Host performs ISA READ cycle immediately following completion of ISA WRITE cycle.
After completion of first embedded 80188 access to FLASH, posted ISA WRITE executes to SRAM;
ISA READ stycle is being held in wait state.
5
6
After completion of posted ISA WRITE cycle, new embedded 80188 access to FLASH begins.
After completion of second embedded 80188 access to FLASH, ISA READ cycle is allowed to proceed
onto memory bus to SRAM; host is still held in wait state.
7
At SRAM READ cycle completion, data is delivered to ISA bus and wait state is exited.
6. Parameter is not included in production test.
7. Parameter only applies when IOCHRDY is deasserted.
136
Am79C930
AMD [ AMD ]
