AMD
P R E L I M I N A R Y
Test Conditions
PCMCIA MEMORY WRITE ACCESS
Parameter
Symbol
Parameter Description
Address setup to WE ↓
Address setup to WE ↑
Min
20
Max
Unit
ns
tAVWL
tAVWH
100
ns
tWMAX
Write recovery time
(Address hold from WE ↑ )
20
140
0
ns
ns
ns
tELWH
tELWL
tGHEH
CE setup to WE ↑
CE setup to WE ↓
CE hold from OE ↑ (READ) or CE
hold from WE ↑ (WRITE)
20
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tGHWL
tWHGL
OE setup to WE ↓
OE hold from WE ↑
WE pulse width
10
tWLWH
tWLWTV
tWTLWTH
tWTHWH
tDVWH
120
35
WAIT valid from WE ↓
WAIT pulse width
Notes 1, 2
53 X TCLKIN
WE hold from WAIT ↑
Data setup to WE ↑
Data hold from WE ↑
Data disabled from OE ↑
Data disabled from WE ↓
Data enabled from WE ↑
Data enabled from OE ↓
0
60
30
tWMDX
tGHQZ
Note 2
Note 2
Note 2
Note 2
90
90
tWLQZ
tWHQNZ
tGLQNZ
5
5
Notes:
1. The max value for this parameter assumes the following worst case situation:
Value
Worst Case
0
1
FLASH and SRAM wait states set at “3.”
Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins
instruction fetch cycle to FLASH memory.
2
PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188
controller access.
3
4
Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle.
After completion of first embedded 80188 access to FLASH, posted PCMCIA WRITE executes to SRAM;
PCMCIA READ stycle is being held in wait state.
5
6
After completion of posted ISA WRITE cycle, new embedded 80188 access to FLASH begins.
After completion of second embedded 80188 access to FLASH, PCMCIA READ cycle is allowed to proceed onto
memory bus to SRAM; host is still held in wait state.
7
At SRAM READ cycle completion, data is delivered to PCMCIA bus and wait state is exited.
2. Parameter is not included in production test.
132
Am79C930
AMD [ AMD ]
