AMD
P R E L I M I N A R Y
Test Conditions
PCMCIA I/O READ ACCESS
Parameter
Symbol
Parameter Description
Address setup to IORD ↓
Address hold from IORD ↑
REG setup to IORD ↓
REG hold from IORD ↑
CE setup to IORD ↓
Min
70
20
5
Max
Unit
tAVIGL
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIGHAX
tRGLIGL
tIGHRGH
tELIGL
0
5
tIGHEH
tIGLIGH
tIGLIAL
CE hold from IORD ↑
IORD width
20
165
0
INPACK ↓ delay from IORD ↓
INPACK ↑ delay from IORD ↑
WAIT ↓ delay from IORD ↓
WAIT width
45
tIGHIAH
tIGLWTL
tWTLWTH
tWTHQV
tIGLQNZ
tIGLQV
45
35
53 X TCLKIN
0
Notes 1, 2
Note 2
Data delay from WAIT ↑
Data enabled from IORD ↓
Data delay from IORD ↓
Data hold from IORD ↑
Data disabled from IORD ↑
0
0
100
20
tIGHQX
tIGHQZ
Note 2
Notes:
1. The max value for this parameter assumes the following worst case situation:
Value
Worst Case
0
1
FLASH and SRAM wait states set at “3.”
Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins
instruction fetch cycle to FLASH memory.
2
PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188
controller access.
3
4
Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle.
After completion of first embedded 80188 access to FLASH, posted PCMCIA WRITE executes to SRAM;
PCMCIA READ stycle is being held in wait state.
5
6
After completion of posted ISA WRITE cycle, new embedded 80188 access to FLASH begins.
After completion of second embedded 80188 access to FLASH, PCMCIA READ cycle is allowed to proceed
onto memory bus to SRAM; host is still held in wait state.
7
At SRAM READ cycle completion, data is delivered to PCMCIA bus and wait state is exited.
2. Parameter is not included in production test.
Am79C930
133
AMD [ AMD ]
