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X1 is connected to a common Crystal Oscillator or a TTL Clock Source. It is not
recommended that X1 be connected to another Receiver’s CLK output.
X2 is grounded.
The DMS pins of all TAXls must be tied in the same state as the DMS pins on the
Transmitters.
The CSTRB/DSTRB pins on each of the Receivers are all active simultaneously. A
timing description for CSTRB and DSTRB is included in Appendix C, TAXI TIP #89-10
TAXI receiver CSTRB and DSTRB pulse width.
The VLTN pin has timing that is identical to the timing of the Data Out and the Com-
mand Out lines. Its connections are specific to each user’s applications.
If CNB is HIGH, the Receiver will catch the next valid byte of data and hold it. It will not
attempt to catch any more data until it sees a Sync command from the Transmitter or
until its CNB goes LOW and then HIGH again.
Fig u re 7 -3
Re c e ive rs in Ca s c a d e Mo d e
12.5 MHz
Crystal
OSC
SERIN–
SERIN+
SERIN–
SERIN–
SERIN+
SERIN+
CLK
X2
X1
X2 X1
DMS
X2 X1
DMS
DMS
IGM
RX1
Am7969
PRIMARY RX
RX2
Am7969
RX3
Am7969
VCC
IGM
CSTRB CMD DATA DSTRB VLTN
IGM
CNB
CNB
CNB
N/C
CSTRB CMD DATA DSTRB VLTN
CSTRB CMD DATA DSTRB VLTN
D23-D16
*Transmission line terminations not shown.
D15-D8
D7-D0
12330E-25
The following section describes the functionality of individual pins:
Th e DS TRB P in
Any one of the DSTRBs may be used as the user’s DSTRB to his system. When an
entire word has been received (signified internally by a Sync from the Transmitter) the
data in the Receivers are latched out to the output ports and all the DSTRBs are raised
(simultaneously) one cycle later. Likewise, if Commands are sent as part of the cascade
word, the CSTRB/DSTRB connections must be made appropriately.
Timing description for receivers in cascade mode is included in Figure 7-4.
78
TAXIchip Integrated Circuits Technical Manual
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