AMD
Fig u re 7 -1
Ca s c a d e d TAXI S ys t e m
Mixed Data
Sources
8
4
DI0–DI7
SEROUT+
SEROUT–
CI0–CI7
STRB ACK
ACK
(Note 2)
TAXI RX #1
TAXI TX #1
TLS DMS
X1 X2
CLK
*
12.5 MHz
From an External
TTL Frequency Source
12.5 MHz
VCC
To Next
CLOCK
SERIN+ SERIN–X1 X2
DMS
CLOCK
SERIN+ SERIN–X1 X2
CNB
DMS
Stage
IGM
VLTN
IGM
CNB TAXI RX #1
TAXI RX #2
DSTRB DO0–DO7 CO0–CO3 CSTRB
(Note 1)
VLTN
DSTRB DO0–DO7 CO0–CO3 CSTRB
8
4
8
4
Data
Destination
Command
Destination
Data
Destination
Command
Destination
Data Path Control Logic
Data Path Control Logic
12330E-1
75
TAXIchip Integrated Circuits Technical Manual