AMD
Fig u re 7 -4
Internal
Re c e ive r Tim in g —8 -Bit Ca s c a d e Mo d e
Clock*
1 1 0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 0 0 1
1 1 0 0 0 1 0 0 0 1
SYNC
SERIN
Serial Data
SYNC
SYNC
DATA 1
DATA 1
DATA 2
DATA 2
DATA N
DATA N
1 1 0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 0 0 1
1 1 0 0 0 1 0 0 0 1
SYNC
SYNC
SYNC
NRZ Data*
CLK OUT
1
2
3
4
5
6
CNB TAXI #1 = 1
IGM TAXI #1 =
CNB TAXI #2
Command
OUT
NO CHANGE
NO CHANGE
NO CHANGE
NO CHANGE
NO CHANGE
NO CHANGE
NO CHANGE
DATA N–1
COMMAND 0
NO CHANGE
NO CHANGE
NO CHANGE
CSTRB OUT
TAXI
#1
DATA OUT
DSTRB OUT
Command
OUT
NO CHANGE
NO CHANGE
NO CHANGE
NO CHANGE
NO CHANGE
NO CHANGE
NO CHANGE
DATA N
NO CHANGE
NO CHANGE
NO CHANGE
CSTRB OUT
DATA OUT
DSTRB OUT
TAXI
#2
NO CHANGE
12330E-26
* Internal Signals
If CNB is HIGH, the Receiver will catch the next valid byte of data and hold it. It will not
attempt to catch any more data until it sees a Sync command from the Transmitter or
until its CNB goes LOW and then HIGH again.
If CNB is held LOW, the Receiver will not attempt to capture any data.
When the Primary Receiver RX1 catches a valid data byte it will raise its IGM (I Got
Mine) so the next Receiver RX2 can catch the next byte and so on down the line. After
all the receivers in the system have received their bytes a Sync must be sent or the next
byte of data will be lost(3)
.
Referring to Figure 7-5 for a system of Cascaded Receivers.
(3)
In the Auto-Repeat Configuration, a Sync is not required.
79
TAXIchip Integrated Circuits Technical Manual
AMD [ AMD ]
