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7 .1 Tra n s m it Ca s c a d e d Da t a w it h a S in g le TAXI Tra n s m it t e r
For systems that require data transfer wider than a single byte, a single TAXI Transmit-
ter can be used to cascade the multiple bytes. This operation allows the data to be
multiplexed onto a single serial link, and then automatically demultiplexed and restored
to the original word width. The TAXI Receiver performs this demux operation automati-
cally when connected in the cascade configuration illustrated in the TAXlchip data sheet
and section 7.2.
The circuit shown in Figure 7-2 illustrates the basic technique that may be used to
control multiplexing of word-wide data into a single TAXI Transmitter.
This circuit assumes that the data to be transmitted is stored in appropriate registers
that are all loaded simultaneously. While many systems will already include these
storage elements, in the diagram these registers are shown as 74ALS374 octal D
flipflops. They could be any register with the appropriate number of bits for the data, and
a three-state controllable output. The registers are connected in a TRISTATE MUX
configuration wherein each output can be selected individually.
To clarify the illustration of the technique, the Command lines are not used, and have
been tied low. In systems that send Commands as part of the data stream, these lines
would be buffered in the same way as the data, except that the unused bits (or bytes)
need to be held low when Data is to be sent.
The controller for the automatic multiplexer consists of a shift register that can be loaded
with a 0 that shifts through and selects each data register in sequence, and strobes the
TAXI Transmitter. In the attached figure, this shift register is a 74LS174, but any
collection of flip-flops would serve as well. The shifter is loaded with a 0 when STROBE,
the signal that loads data into the registers, is a 1. The NAND gate (U1) at the input of
the first flip-flop assures that only a single 0 is possible while the registers are being
selected.
STRB for the Transmitter is derived from the CLK output of Transmitter, and is gated by
the same signals that select the data. It is important that no glitches appear on the TAXI
STRB input, since that will cause false data to be sent, and will disrupt the information
transfer. To assure that any race-caused glitches appearing at the output of the four
input NAND gate (U2) are suppressed, the counter must be clocked on the falling edge
of the CLK. This assures that, during the time the outputs are changing, the low on the
CLK input of the two input NAND gate (U3) will suppress anything happening on the
other input. When CLK rises, it will be the only signal active, and there should be no
false strobes. This configuration also assures the longest possible setup time for the
output of the data registers, since the STRB happens immediately before the outputs
change, and a full byte time before they change again. The other gates (U4, U5, U6) are
only buffer and inverters used to assure proper signal sense, and fanout. They may not
be needed in all systems.
Only four stages of shift register are required to select the four data registers, and the
fifth stage shown in the figure is used to provide the SYNC character required for some
cascade systems. The output of the fifth stage (ACK1 stands for one SYNC) is used to
ACK systems that require a SYNC between data words. The output of the fourth stage
(ACK0 stands for no SYNC) can be used for ACK in systems that expect to send
contiguous data, and no SYNCs between words (auto-repeat cascade). Either of these
outputs can be connected back to the DATA STRB input if the system is to run automati-
cally, as in data sampling systems.
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TAXIchip Integrated Circuits Technical Manual
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