AMD
Fig u re 7 -5
CNB a n d IGM P ro p a g a t in g Do w n Ca s c a d e d Re c e ive rs
Time
Serial
Data
Sync
Data 1
Data 2
Data 3
Sync
CNB1 =
VCC
a
b
c
d
t46
IGM1
CNB2
IGM2
CNB3
IGM3 =
N/C
12330E-27
Note: Half of the byte is sufficient for the Receiver to decide whether the byte is a Sync or Data.
When CNB on the first Receiver is raised (Figure 7-3 it is tied to Vcc), its IGM does not
follow until the first half of a non-Sync byte is detected in its SERIN. Note that if a Sync
is detected, IGM does not go HIGH, since it is a Sync that makes IGM fall.
The IGM on RX1 rises when it sees a non-Sync byte, then since it is tied to the CNB of
RX2. RX2 will now be ready to accept the next byte of data.
RX2 will now wait for the next non-Sync byte to come down the SERIN lines. During this
time all the other downstream receivers will ignore the data on the SERIN lines because
their CNBs are still LOW. In the same way the upstream (Primary) Receiver will ignore
the SERIN lines because it has already caught one byte and thus it will continue to
ignore the data until it sees another Sync.
The IGM on RX2 rises when it sees the second non-Sync byte.
In this fashion, each Receiver will sequentially get ready to receive data as the CNBs
propagate down the IGMs.
When the first Receiver sees a Sync, it will lower its IGM which is connected to RX2’s
CNB which will lower its IGM and RX3’s CNB and so on. In this way the LOW IGM will
also propagate down all the Cascaded Downstream Receivers. CNB falling to IGM
falling is t46 ns.
In normal Cascade mode, the CNB on RXl is tied HIGH and thus, a Sync has to be sent
after all the receivers are full to ensure that RX1 is reset to accept the next byte of data.
80
TAXIchip Integrated Circuits Technical Manual
AMD [ AMD ]
