DEVICE SPECIFICATION
S5933
PCI CONTROLLER
Table 4-4. PCI Command Register
Bit
Description
15:10
9
Reserved. Equals all 0’s.
Fast Back-to-Back Enable. The S5933 does not support this function. This bit must be set to zero.
This bit is cleared to a 0 upon RESET#.
8
System Error Enable. When this bit is set to 1, it permits the S5933 controller to drive the open drain
output pin, SERR#. This bit is cleared to 0 upon RESET#. The SERR# pin driven active normally
signifies a parity error on the address/control bus.
7
6
WaitCycleEnable.Thisbitcontrolswhetherthisdevicedoesaddress/datastepping.SincetheS5933
controller never uses stepping, it is hardwired to 0.
Parity Error Enable. This bit, when set to a one, allows this controller to check for parity errors. When
a parity error is detected, the PCI bus signal PERR# is asserted. This bit is cleared (parity testing
disabled) upon the assertion of RESET#.
5
4
Palette Snoop Enable. This bit is not supported by the S5933 controller and is hardwired to 0. This
feature is used solely for PCI-based VGA devices.
Memory Write and Invalidate Enable. This bit allows certain Bus Master devices to use the Memory
Write and Invalidate PCI bus command when set to 1. When set to 0, masters must use the Memory
Write command instead. The S5933 controller does not support this command when operated as a
master and therefore it is hardwired to 0.
3
Special Cycle Enable. Devices which are capable of monitoring special cycles can do so when this
bit is set to 1. The S5933 controller does not monitor (or generate) special cycles and this bit is
hardwired to 0.
2
1
BusMasterEnable.Thisbit,whensettoaone,allowstheS5933controllertofunctionasabusmaster.
This bit is initialized to 0 upon the assertion of signal pin RESET#.
Memory Space Enable. This bit allows the S5933 controller to decode and respond as a target for
memory regions that may be defined in one of the five base address registers. (See Section 4.11.)
This bit is initialized to 0 upon the assertion of signal pin RESET#.
0
I/O Space Enable. This bit allows the S5933 controller to decode and respond as a target to I/O cycles
which are to regions defined by any one of the five base address registers. (See Section 4.11). This
bit is initialized to 0 upon the assertion of signal pin RESET#.
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