DEVICE SPECIFICATION
S5933
PCI CONTROLLER
Table 4-5. PCI Status Register
Bit
Description
15
14
13
12
11
10:9
8
Detected Parity Error. This bit is set whenever a parity error is detected. It functions independently
from the state of Command Register Bit 6. This bit may be cleared by writing a 1 to this location.
Signaled System Error. This bit is set whenever the device asserts the signal SERR#. This bit can be
reset by writing a 1 to this location.
Received Master Abort. This bit is set whenever a bus master abort occurs. See Section 8.1.4.3 for
further definition of a master abort. This bit can be reset by writing a 1 to this location.
Received Target Abort. This bit is set whenever this device has one of its own initiated cycles
terminated by the currently addressed target. This bit can be reset by writing a 1 to this location.
Signaled Target Abort. This bit is set whenever this device aborts a cycle when addressed as a target.
This bit can be reset by writing a 1 to this location.
Device Select Timing. These bits are read-only and define the signal behavior of DEVSEL# from this
device when accessed as a target.
Data Parity Reported. This bit is set upon the detection of a data parity error for a transfer involving
the S5933 device as the master. The Parity Error Enable bit (D6 of the Command Register) must be
set in order for this bit to be set. Once set, it can only be cleared by either writing a 1 to this location
or by the assertion of the signal RESET#.
7
Fast Back-to-back Capable. When equal to 1, this indicates that the device can accept fast back-to-
back cycles as a target.
6:0
Reserved. Equal all 0’s.
Applied Micro Circuits Corporation
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6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
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