DEVICE SPECIFICATION
S5933
PCI CONTROLLER
4.4 PCI STATUS REGISTER (PCISTS)
This 16-bit register contains the PCI status informa-
tion. The function of this register is defined by the
PCI specification and its implementation is required
of all PCI devices. Only some of the bits are used by
this device; those which are not used are hardwired
to 0. Most status bits within this register are desig-
nated as “write clear,” meaning that in order to clear
a given bit, the bit must be written as a 1. All bits
written with a 0 are left unchanged. These bits are
identified in Figure 4-4 as (R/WC). Those which are
Read Only are shown as (RO) in Figure 4-4.
Register Name:
Address Offset:
PCI Status
06h-07h
Power-up value:
Boot-load:
0080h
not used
Attribute:
Read Only (RO), Read/Write
Clear (R/WC)
Size:
16 bits
Figure 4-4. PCI Status Register
15
X
14
X
13
X
12
X
11
X
10
0
9
0
8
7
6
0
X
0
Reserved (RO) = 00's
Reserved (RO)
Fast Back-to-Back (RO)
Data Parity Reported (R/WC)
DEVSEL# Timing Status (RO)
0 0 = Fast (S5933)
0 1 = Medium
1 0 = Slow
1 1 = Reserved
Signaled Target Abort (R/WC)
Received Target Abort (R/WC)
Received Master Abort (R/WC)
Signaled System Error (R/WC)
Detected Parity Error (R/WC)
Applied Micro Circuits Corporation
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