S3098 – SONET/SDH/ATM OC-192 1:16
Low Power Receiver w/CDR/Postamp
Parallel Output Clock (POCLKP/N)
The Parallel Output Clock (POCLKP/N) LVDS output is
an internally regenerated clock which is used to transfer
demultiplexed data from an internal holding register to
the output register, which drives POUTP/N [15:0]. This
clock is synchronized with the parallel output data and
must be inverted (cross traces on printed wire board) to
be OIF compliant from the module perspective. The
parallel outputs are internally terminated with 330
Ω
to
ground (GND).
Parallel Output Data (POUTP/N[15:0])
The Parallel Output Data (POUTP/N[15:0]) LVDS out-
puts are re-timed data, output from the Demultiplexer
(Demux) at a rate of 622.08 Mbps (or equivalent FEC
rate). Bit 15 is the most significant bit and is the first
received. The data is re-timed and synchronized to the
Parallel Output Clock (POCLKP/N). These outputs are
internally terminated with 330
Ω
to GND. This bus is
typically connected to a framer, mapper or digital wrap-
per ( e.g. G ANG ES II, G AN G E S, ME KO N G, or
HUDSON).
Revision NC - Oct 17, 2001
DEVICE SPECIFICATION
Lock Detect (LOCKDET)
When the LVCMOS output Lock Detect (LOCKDET)
signal is inactive (Low), it indicates that the incoming
data stream has failed the frequency test, as dictated
by the PLL, or LCKREFN has been asserted Low, or
SDLVCMOSN/SDLVPECL has been asserted. This
test is used to determine whether or not serial input
activity is valid data. When LOCKDET is active, the
PLL is locked to the data stream.
Recovered 622.08 MHz Clock (RX622MCKP/N)
The LVDS 622.08 MHz Clock (or equivalent FEC rate)
(RX622MCKP/N) is the clock which is recovered from
the input data stream. During loss-of-signal conditions
or when LCKREFN has been asserted, this output
clock is derived from the Reference Clock Input (REF-
CLKP/N). This is internally terminated with 330
Ω
to
ground (GND).
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