S3098 – SONET/SDH/ATM OC-192 1:16
Low Power Receiver w/CDR/Postamp
S3098 PIN DESCRIPTION
Serial Data In (SERDATIP/N)
The Serial Data In (SERDATIP/N) pins are differential
Current Mode Logic (CML) inputs. They receive inputs
from an optics module or other upstream logic device.
The S3098 extracts the clock from the SERDATIP/N
inputs and provides a recovered clock (POCLKP/N)
with re-timed parallel data. These pins are internally
biased and terminated 100
Ω
line-to-line.
Reference Clock (REFCLKP/N)
The Reference Clock (REFCLKP/N) pins are an
LVPECL 155.52 MHz (or equivalent FEC rate) input
used to establish the initial operating frequency of the
clock recovery PLL. The REFCLKP/N is also used in
the absence of data to maintain PLL lock. This input is
internally biased and terminated 100
Ω
line-to-line.
Most implementations may require AC coupling. See
Ta b l e 1 ,
R e f e r e n c e F r e q u e n c y,
f o r R E F C L K
requirements.
Loop Filter (CAP1, CAP2)
The external loop filter capacitor and resistors are con-
nected to the CAP1 and CAP2 pins. These devices
should be surrounded by a ground shield. Component
values should be as stated in Table 18,
External Loop
Filter Components.
Lock to Reference (LCKREFN)
The LVCMOS Lock to Reference (LCKREFN) signal,
when asserted Low, will force the PLL to lock to the
local Reference Clock (REFCLK) as well as de-assert
LOCKDET.
Signal Detect (SDLVPECLN/SDLVCMOSN)
Two types of signal detect inputs (SDLVPECLN/
SDLVCMOSN) are provided, LVPECL and LVCMOS.
The LVPECL input should be driven by optical trans-
ceivers with an LVPECL signal detect output, and the
LVCMOS input should be driven by optical transceiv-
ers with an LVCMOS signal detect output. The
LVPECL input is internally pulled down. These inputs
may be used with optics modules that are either active
Low or active High for loss of light.
An optics module with an LVPECL output should be
connected to the SDLVPECLN input. Connect SDLVC-
M O S N a s s h o w n i n Ta b l e 2 ,
S D LV C M O S N
Connections when using the SDLVPECLN Input.
An optics module with an LVCMOS output should be
connected to the SDLVCMOSN input. Connect
SDLVPECLN as shown in Table 3,
SDLVPECLN Con-
nections when using the SDLVCMOSN Input.
Reset (RSTB)
SDLVCMOSN
Revision NC - Oct 17, 2001
DEVICE SPECIFICATION
Table 1. Reference Frequency
Input Data Rate
(SERDATIP/N)
9.953 Gbps
10.234 Gbps
10.317 Gbps
10.402 Gbps
10.488 Gbps
10.575 Gbps
10.664 Gbps
10.709 Gbps
Required Reference
Frequency (REFCLK)
155.52 MHz
159.91 MHz
161.20 MHz
162.53 MHz
163.87 MHz
165.23 MHz
166.63 MHz
167.33 MHz
Table 2. SDLVCMOSN Connections when using
SDLVPECLN Input
Optics Device
Active Low for
loss of light
Connect to GND
Optics Device
Active High for
loss of light
Connect to
V
CC_2.5V
Table 3. SDLVPECLN Connections when using
SDLVCMOSN Input
Optics Device
Active Low for
loss of light
SDLVPECLN
Connect to GND
Optics Device
Active High for loss
of light
Connect to
V
CC_3.3V1
1. Connecting to V
CC_3.3 V
is permitted under static conditions.
The master Reset (RSTB) LVCMOS pin, when
asserted Low, asynchronously resets the device. For
normal operation, connect to V
CC_2.5 V
through a 10 kΩ
resistor. This should be active for 100 ns to accurately
reset the device.
Factory Test (TSTSIG, TESTB)
Two LVCMOS factory test (TSTSIG, TESTB) pins are
for test factory purposes only. For normal operation,
connect to V
CC_2.5 V
through a 10 kΩ resistor.
6
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