Revision NC - Oct 17, 2001
S3098 – SONET/SDH/ATM OC-192 1:16
Low Power Receiver w/CDR/Postamp
DEVICE SPECIFICATION
Table 5. Output Pin Descriptions and Assignment
Pin Name
POCLKP
Level
I/O
Pin #
Description
LVDS
O
B10
B9
Parallel Output Clock. Regenerated 622.08 MHz (or equivalent FEC rate)
differential output clock, synchronized to the parallel output data. (See Fig-
ure 5, Parallel Data Output Delay from POCLK). Internally terminated with
330 Ω to GND.
POCLKN
POUT0P
POUT0N
POUT1P
POUT1N
POUT2P
POUT2N
POUT3P
POUT3N
POUT4P
POUT4N
POUT5P
POUT5N
POUT6P
POUT6N
POUT7P
POUT7N
POUT8P
POUT8N
POUT9P
POUT9N
POUT10P
POUT10N
POUT11P
POUT11N
POUT12P
POUT12N
POUT13P
POUT13N
POUT14P
POUT14N
POUT15P
POUT15N
LVDS
O
N2
N3
P3
P4
N4
N5
P5
P6
N6
N7
P7
P8
N8
N9
P9
P10
M11
M12
N12
N13
N14
M14
L13
K13
K14
J14
H14
G14
G13
F13
F14
E14
Parallel Output Data. Re-timed data from the Demultiplexer (DeMUX) at a
rate of 622.08 Mbps (or equivalent FEC rate). POUTP/N15 is the most sig-
nificant bit (corresponding to bit 1 of each word, the first bit received.)
POUTP/N0 is the least significant bit corresponding to bit 16 of each word,
the last bit received). Internally terminated with 330 Ω to GND.
LOCKDET
LVCMOS
LVDS
O
O
A12
Lock Detect. Active High. Clock recovery indicator. Active when the inter-
nal clock recovery has locked onto the incoming data stream. LOCKDET is
an asynchronous output.
RX622MCKP
RX622MCKN
B11
A11
622.08 MHz Clock (or equivalent FEC rate) derived from VCO clock. Inter-
nally terminated with 330 Ω to GND.
10
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