S3098 – SONET/SDH/ATM OC-192 1:16
Low Power Receiver w/CDR/Postamp
S3098 FUNCTIONAL DESCRIPTION
Receiver Description
The S3098 receiver chip provides the first stage of the
digital processing of a receive SONET OC-192 bit-
serial stream. It converts the bit-serial 9.953 Gbps data
stream into a 622.08 Mbps (or equivalent FEC rate)
16-bit parallel data format.
Postamp
The S3098 limiting postamp takes the differential
serial data from the SERDATIP/N pins and provides
36 dB of small signal gain. The input to the postamp
can be either AC or DC coupled.
Clock Recovery
The clock recovery circuitry generates a clock that is
the same frequency as the incoming data bit rate at
the serial data input. The clock is phase aligned by a
Phase Lock Loop (PLL) so that it samples the data in
the center of the data eye pattern.
The Clock and Data Recovery (CDR) extracts a syn-
chronous signal from the serial data input using a PLL.
The PLL consists of a Voltage Controlled Oscillator
(VCO), Phase/Frequency Detectors (PFD), and a loop
filter.
The frequency detector ensures predictable lock-up
conditions. It is used during acquisition and serves as
a means to pull the VCO into the range of the data rate
at which the phase detector is capable of acquiring
lock.
The phase detector used in the CDR is designed to
give minimum static phase error of the PLL. When a
transition has occurred, the value of the sample in the
vicinity of the transition tells whether the VCO clock
leads or lags the incoming data, and the phase detec-
tor produces a binary output accordingly.
When a loss-of-signal condition exists, Signal Detect
(SDLVCMOSN or SDLVPECLN) will be de-asserted,
and the PLL locks onto the Reference Clock (REF-
CLK) to provide a steady output clock. There are two
pins (CAP1 and CAP2) to connect the external capaci-
tor and resistors in order to adjust the PLL loop
performance.
The phase relationship between the edge transitions
of the data and those of the generated clock are com-
pared by a phase/frequency discriminator. Output
pulses from the discriminator indicate the required
direction of phase corrections. These pulses are
Revision NC - Oct 17, 2001
DEVICE SPECIFICATION
smoothed by an integral loop filter. The output of the
loop filter controls the frequency of the Voltage Con-
trol led O sc illator ( VCO ), whic h gener ates the
recovered clock.
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET data
signal.
The total loop dynamics of the clock recovery PLL
yield a jitter tolerance that exceeds the minimum toler-
ance proposed for SONET equipment by the Telcordia
TA-NWT-000253 standard.
Lock Detect
The S3098 contains a lock detect circuit, which moni-
tors the integrity of the serial data inputs. If the
received serial data fails the frequency test, the PLL
will be forced to lock to the local reference clock. This
will maintain the correct frequency of the recovered
clock output under loss-of-signal or loss-of-lock condi-
tions. If the recovered clock frequency deviates from
the local reference clock frequency by more than the
typical value stated in Table 8,
Performance Specifica-
tions,
the PLL will be declared out of lock. The phase
detect circuit will poll the input data stream in an
attempt to reacquire lock to data. If the recovered
clock frequency is determined to be within the typical
value stated in Table 8,
Performance Specifications,
the PLL will be declared in lock, and the lock detect
output will go active. A de-asserted signal detect
(SDLVCMOSN or SDLVPECLN) will also cause an
out-of-lock condition.
Serial-to-Parallel Converter
The serial-to-parallel converter consists of three 16-bit
registers. The first is a serial-in, parallel-out shift regis-
ter, which performs the serial-to-parallel conversion.
The second is a 16-bit internal holding register, which
transfers data from the serial-to-parallel register on
byte boundaries. On the falling edge of the Parallel
Output Clock (POCLK), the data in the holding register
is transferred to an output holding register, which
drives Parallel Output Data (POUTP/N[15:0]).
Power Sequencing
In order to avoid latch up, the following power-up
sequence is required. Apply GND first, next -5.2 V,
then the positive supplies, +2.5 V and +3.3 V. These
two positive supplies can be brought up simulta-
neously or in any order.
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