S3098 – SONET/SDH/ATM OC-192 1:16
Low Power Receiver w/CDR/Postamp
Table 4. Input Pin Description and Assignment
Pin Name
SERDATIP
SERDATIN
REFCLKP
REFCLKN
CAP1
CAP2
LCKREFN
Level
Diff.
CML
Diff.
LVPECL
Analog
I/O
I
Pin #
G1
J1
B1
C1
B4
C4
C14
Revision NC - Oct 17, 2001
DEVICE SPECIFICATION
Description
Serial Data Input.
Differential high frequency serial data input to limiting
postamp for small signal gain. Internally biased and terminated 100
Ω
line-
to-line.
Reference Clock.
Differential reference clock input at 155.52 MHz (or equiv-
alent FEC rate). The PLL will lock onto this reference in the absence of serial
input data. Internally biased and terminated 100
Ω
line-to-line.
Loop Filter.
The external loop filter capacitor and resistors are connected to
these pins. Used to adjust the loop filter performance. See Figure 12,
External
Loop Filter
and Table 18,
External Loop Filter Components.
Lock to Reference.
Active Low. When active, the PLL will be forced to lock
to the local reference clock input (REFCLK). If unused, connect to V
CC_2.5 V
through a 10 kΩ resistor for normal operation.
Master Reset.
Active Low. Reset input for the device. For correct reset, this
input must be asserted Low for 100 ns. Connect to V
CC_2.5 V
through a 10
kΩ resistor if not used.
Test Enable.
Active Low. Used during production test to bypass the VCO in
the PLL. Connect to V
CC_2.5 V
through a 10 kΩ resistor for normal operation.
Test Input.
Active Low. Signal used for production test. Connect to V
CC_2.5 V
through a 10 kΩ resistor for normal operation.
Signal Detect.
A Single-Ended 10 K LVPECL input to be driven by the
external optical receiver module to indicate a loss of received optical power.
This input may be utilized by an optics module that is active Low or active
High for loss of light. For an active High device, SDLVCMOSN must be con-
nected to V
CC_2.5 V
through a 10 kΩ resistor. For an active Low optics mod-
ule, the SDLVCMOSN input must be connected to GND. The optics module
LVPECL signal detect output may be directly connected to the SDLVPECLN
input. This input is internally pulled Low. When a loss of light condition
occurs, the internal PLL will be forced to lock to the REFCLK input signal.
Signal Detect.
A LVCMOS input to be driven by the external optical
receiver module to indicate a loss of received optical power. This input may
be utilized by an optics module that is active Low or active High for loss of
light. For an active Low device, SDLVPECLN must be connected to GND.
For an active High optics module, the SDLVPECLN input must be con-
nected to V
CC_3.3 V.
through a 10 kΩ resistor. The optics module LVCMOS
signal detect output may be directly connected to the SDLVCMOSN input.
When a loss of light condition occurs, the internal PLL will be forced to lock
to the REFCLK input signal.
I
I
LVCMOS
I
RSTB
LVCMOS
I
A7
TESTB
LVCMOS
I
C6
TSTSIG
LVCMOS
I
A6
SDLVPECLN
Single-
Ended
LVPECL
I
A9
SDLVCMOSN
LVCMOS
I
B13
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
