Revision NC - Oct 17, 2001
S3098 – SONET/SDH/ATM OC-192 1:16
Low Power Receiver w/CDR/Postamp
DEVICE SPECIFICATION
Table 8. Performance Specifications
Parameter
Min.
9.953
-100
Typ
Max
10.709
100
Units
GHz
ppm
Conditions
Nominal VCO Center Frequency
155.52 MHz (or equivalent FEC rate)
Reference Clock Frequency Toler-
ance
± 20 ppm is required to meet
SONET output frequency spec-
ification.
155.52 MHz (or equivalent FEC rate)
Reference Clock Input Duty Cycle
40
60
0.8
-10
% of UI
ns
155.52 MHz (or equivalent FEC rate)
Reference Clock Rise and Fall Times
0.080
20% to 80% of amplitude.
DC - 10 GHz
SERDATIP/N Input Return Loss (S
(when driven differentially)
)
dB
11
SERDATIP Input Return Loss (S
)
-5
dB
ms
DC - 10 GHz
11
(when driven single-ended using the
termination scheme in Figure 13)
Acquisition Lock Time (RSTB deas-
sertion to LOCKDET assertion)
4.5
Minimum transition density of
50%. Guaranteed, but not
tested. With device already
powered up and valid REFCLK.
Frequency difference at which the
±440
±220
±600
±300
±732
±366
ppm
ppm
PLL goes out-of-lock (REFCLK com-
pared to the divided down VCO
clock).
Frequency difference at which receive
PLL goes into lock (REFCLK com-
pared to the divided down VCO
clock).
J
Jitter Tolerance (SERDATIP/N)
15
15/(f ÷ 2400)
1.5
UI
UI
UI
UI
UI
10 Hz-2.4 kHz (Sinusoidal)
2.4 kHz-24 kHz (Sinusoidal)
24 kHz-400 kHz (Sinusoidal)
400 kHz-4 MHz (Sinusoidal)
4 MHz-1 GHz (Sinusoidal)
tol
(p-p)
(p-p)
(p-p)
(p-p)
(p-p)
3
1.5/(f ÷ 400 x 10 )
0.15
L
Consecutive identical digits at
80
bits
Number of bits with no transi-
tions. (SONET spec is 75 bits
max.)
cid
Serial Data Input
14
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
