S3038
SONET/SDH/ATM OC-12 QUAD TRANSCEIVER
Table 8. Receiver Input Signals Pin Assignment and Description
Pin Name
Level
I/O
Pin #
Description
RSDA0P
RSDA0N
Diff.
LVPECL
I
D5
C5
Primary differential LVPECL compatible inputs for channel A.
RSDA0P is the positive input, RSDA0N is the negative. Internally
biased to VDD-1.3V for AC coupled applications.
RSDA1P
RSDA1N
Diff.
LVPECL
I
D4
B3
Secondary differential LVPECL compatible inputs for channel A.
RSDA1P is the positive input, RSDA1N is the negative. Internally
biased to VDD-1.3V for AC coupled applications.
RSDASEL
TTL
I
I
A3
Channel A input select control. Low selects input RSDA0, High
selects RSDA1. (Internal pull-up when not connected.)
RSDB0P
RSDB0N
Diff.
LVPECL
C6
B5
Primary differential LVPECL compatible inputs for channel B.
RSDB0P is the positive input, RSDB0N is the negative. Internally
biased to VDD-1.3V for AC coupled applications.
RSDB1P
RSDB1N
Diff.
LVPECL
I
C7
D7
Secondary differential LVPECL compatible inputs for channel B.
RSDB1P is the positive input, RSDB1N is the negative. Internally
biased to VDD-1.3V for AC coupled applications.
RSDBSEL
TTL
I
I
A5
Channel B input select control. Low selects input RSDB0, High
selects RSDB1. (Internal pull-up when not connected.)
RSDC0P
RSDC0N
Diff.
LVPECL
A10
B9
Primary differential LVPECL compatible inputs for channel C.
RSDC0P is the positive input, RSD is the negative. Internally
biased to VDD-1.3V for AC coupled applications.
RSDC1P
RSDC1N
Diff.
LVPECL
I
A8
A9
Secondary differential LVPECL compatible inputs for channel C.
RSDC1P is the positive input, RSDC1N is the negative. Internally
biased to VDD-1.3V for AC coupled applications.
RSDCSEL
TTL
I
I
C9
Channel C input select control. Low selects input RSDC0, High
selects RSDC1. (Internal pull-up when not connected.)
RSDD0P
RSDD0N
Diff.
LVPECL
C10
D10
Primary differential LVPECL compatible inputs for channel D.
RSDD0P is the positive input, RSDD0N is the negative. Internally
biased to VDD-1.3V for AC coupled applications.
RSDD1P
RSDD1N
Diff.
LVPECL
I
C11
B12
Secondary differential LVPECL compatible inputs for channel D.
RSDD1P is the positive input, RSDD1N is the negative. Internally
biased to VDD-1.3V for AC coupled applications.
RSDDSEL
TTL
I
I
B11
Channel D input select control. Low selects input RSDD0, High
selects RSDD1. (Internal pull-up when not connected.)
OOFA
OOFB
OOFC
OOFD
LVTTL
U14
T16
P17
K17
Out of frame indicator used to enable framing pattern detection
logic in the S3038. The framing pattern detection logic is enabled
by a rising edge on OOF, and remains enabled until frame
boundary is detected or when OOF is set low, whichever is longer.
OOF is an asynchronous signal with a minimum pulse width of
one POCLK period. Rising edge on OOF is required after RESET
to initialize the chip.
SDTTLA
SDTTLB
SDTTLC
SDTTLD
LVTTL
I
U15
R16
N17
J16
LVTTL Signal Detect. Active High (logic 1). When SDTTL is
inactive, the data on the RSDP/N pins will be internally forced to
a constant zero. When SDTTL is active, data on the RSDP/N pins
will be processed normally.
16
September 16, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
