SONET/SDH/ATM OC-12 QUAD TRANSCEIVER
S3038
Table 7. Receiver Output Signals Pin Assignment and Descriptions (Continued)
Pin Name
Level
I/O
Pin #
Description
POUTD0
POUTD1
POUTD2
POUTD3
POUTD4
POUTD5
POUTD6
POUTD7
TTL
O
U11
R10
U9
R9
T9
U8
U7
T8
Channel D Receiver Data Outputs. Parallel data on this bus is
valid on the rising edge of POCLKDP.
FPD
TTL
TTL
O
O
U6
Frame Pulse. A High on this output indicates that valid data has
been detected and is present on the Parallel Data Output
POUTD[7:0].
POCLKDP
POCLKDN
T10
U10
Receive Data Clock. Parallel receive data, POUTD[7:0] are valid
on the rising edge of POCLKDP.
15
September 16, 1999 / Revision B