S3038
SONET/SDH/ATM OC-12 QUAD TRANSCEIVER
Table 4. Transmitter Input Signals Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin # Description
PINA0
PINA1
PINA2
PINA3
PINA4
PINA5
PINA6
PINA7
TTL
I
P12
R12
T13
T12
U13
P11
R11
T11
Transmit Data for Channel A. Parallel data on this bus is clocked
in on the rising edge of PICLKA or REFCLK.
PICLKA
TTL
TTL
I
I
U12
Transmit Data Clock A. This signal is used to clock data on
PINA[7:0]. This signal can also be used to clock data on
PINB[7:0], PINC[7:0] and PIND[7:0].
PINB0
PINB1
PINB2
PINB3
PINB4
PINB5
PINB6
PINB7
R15
P14
T15
R14
U17
U16
P13
T14
Transmit Data for Channel B. Parallel data on this bus is clocked
in on the rising edge of PICLKA, PICLKB or REFCLK.
PICLKB
TTL
TTL
I
I
R13
Transmit Data Clock B. This signal is used to clock data on
PINB[7:0].
PINC0
PINC1
PINC2
PINC3
PINC4
PINC5
PINC6
PINC7
M15
N16
M14
R17
P16
N15
T17
N14
Transmit Data for Channel C. Parallel data on this bus is clocked
in on the rising edge of PICLKA, PICLKC or REFCLK.
PICLKC
TTL
TTL
I
I
P15
Transmit Data Clock C. This signal is used to clock data on
PINC[7:0].
PIND0
PIND1
PIND2
PIND3
PIND4
PIND5
PIND6
PIND7
L17
K16
K15
K14
M17
L16
M16
L15
Transmit Data for Channel D. Parallel data on this bus is clocked
in on the rising edge of PICLKA, PICLKD, or REFCLK.
PICLKD
TTL
I
L14
Transmit Data Clock D. This signal is used to clock data on
PIND[7:0].
12
September 16, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
