SONET/SDH/ATM OC-12 QUAD TRANSCEIVER
S3038
Table 5. Transmitter Output Signals Pin Assignment and Descriptions
Pin Name
Level I/O
Pin # Description
TSDA0P
TSDA0N
Diff.
LVPECL
O
O
O
O
O
O
O
O
O
A17
B17
Primary high speed serial outputs for Channel A.
TSDA1P
TSDA1N
Diff.
LVPECL
E14
D16
Secondary high speed serial outputs for Channel A.
Primary high speed serial outputs for Channel B.
Secondary high speed serial outputs for Channel B.
Primary high speed serial outputs for Channel C.
Secondary high speed serial outputs for Channel C.
Primary high speed serial outputs for Channel D.
Secondary high speed serial outputs for Channel D.
TSDB0P
TSDB0N
Diff.
LVPECL
C17
D17
TSDB1P
TSDB1N
Diff.
LVPECL
F14
F15
TSDC0P
TSDC0N
Diff.
LVPECL
F16
E17
TSDC1P
TSDC1N
Diff.
LVPECL
G15
G14
TSDD0P
TSDD0N
Diff.
LVPECL
F17
G17
TSDD1P
TSDD1N
Diff.
LVPECL
H14
H15
PCLK
TTL
J14
TTL output clock at the parallel data rate. This clock is provided
for use by the up-stream circuitry.
Table 6. Transmitter Control Signals Pin Assignment and Descriptions
Pin Name
Level I/O
Pin # Description
CH_LOCK
TTL
TTL
I
I
E4
Channel Lock. Parallel input mode control. Active High. When
active, this signal locks all four channels together.
TMODE
B13
Transmit Mode Control. When TMODE is Low, REFCLK is used
to clock data on PINx[7:0]. When TMODE is High, PICLKx is used
to clock data into the S3038. In channel lock mode, all four
channels are clocked by PICLKA. In independent mode (CHAN-
LOCK LOW) each channel is clocked by its respective PICLK.
CLKSEL
REFCLK
RESET
TTL
TTL
TTL
I
I
I
C12
H17
C15
REFCLK Select input. This signal configures the PLL for the
appropriate REFCLK frequency. When CLKSEL = 0, the REFCLK
frequency should equal the 32-bit parallel rate. When CLKSEL =
1, the REFCLK frequency should be 1/2 the parallel data rate.
Reference clock used for the transmit VCO and as a frequency
check for the clock recovered from the receiver serial data.
REFCLK can also be used to clock the input data of all four
channels.
When Low, the S3038 is held in reset. The receiver PLL is forced
to lock to the REFCLK. The FIFO's are initialized on the rising
edge of RESET. When High, the S3038 operates normally.
Note: All inputs have internal pull-up networks.
September 16, 1999 / Revision B
13
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
