SONET/SDH/ATM OC-12 QUAD TRANSCEIVER
S3038
Table 9. Receiver Control Signals Pin Assignment and Descriptions
Pin Name
Level I/O
Pin # Description
DLEB
TTL
I
D14
Diagnostic Loopback Enable. When Low, input source is
determined by the RSDSEL for each channel. When High, the
serial output for each channel is looped back to its input.
TSD0XP/N and TSD1XP/N are squelched when DLEB = HIGH.
Table 10. Power and Ground Pin Assignments
No.
Pin Name
Aliases
Pin # Description
Signals
AVDD
VDDAx
5
A1 A6 C8 Analog Power (VDD) low noise.
A13 A16
AVSS
VDD
VSS
VSSAx
VDDx
5
5
C4 B7 B8 Analog Ground (VSS).
D11 B15
B4 B6 D9 Power for high speed circuitry (VDD).
A12 A15
VSSx
VSSSUBx
10
A2 A4 D6 Ground for high speed circuitry (VSS).
A7 D8
A11 B10
C13 A14
B14
PVDD
PECLPWR
PECLGND
4
D15 E15 PECL Power (VDD).
E16 G16
PVSS
DVDD
1
9
C16
PECL Ground (VSS).
DIGPWR
DIGPWR1
B1 B2 C2 Core circuitry power (VDD).
D3 D12
E3 L4 J17
P9
DVSS
DIGGND
DIGGND1
DIGGNDS
10
B16 C1 Core circuitry ground (VSS).
D2 C3 R3
F4 N4 J15
H16 P10
TVDD
TVSS
TTLPWR
TTLGND
8
E1 N3 G4 Power for TTL I/O (VDD).
H4 K4 P5
P7 P8
10
D1 E2 F3 Ground for TTL I/O (VSS).
L3 J4 M4
P4 R4 P6
R8
Total Pwr/Gnd
67
8
NC
G1 G3 K3 Not connected.
P2 P3 T2
T6 T7
CAP1
CAP2
2
D13
C14
Pins for external loop filter capacitor and resistors. See Figure
20.
17
September 16, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
