S3038
SONET/SDH/ATM OC-12 QUAD TRANSCEIVER
Table 11. Performance Specifications
Parameter
Min
Typ
Max
Units
Condition
Nominal VCO
Center Frequency
622.08
MHz
Data Output Jitter
STS-12
–38.88 MHz Ref.Clk.
–77.76 MHz Ref Clk.
UI (rms)
ppm
rms jitter, in lock
0.01
0.0075
Reference Clock Frequency
Tolerance*
Required to meet SONET output
frequency specification
-20
+20
OC-12/STS-12
Capture Range
Lock Range
±200
±12%
ppm
With respect to fixed reference
frequency
Minimum transition density of
20%
Acquisition Lock Time
16
µsec
With device already powered up
and valid ref. clk.
Reference Clock
Input Duty Cycle
30
70
%
Reference Clock Rise & Fall
Times
2.0
ns
20% to 80% of amplitude
Frequency difference at which
the PLL goes out of lock
(REFCLK compared to the
divided down VCO clock)
250
250
290
290
330
ppm
ppm
Frequency difference at which
the receive PLL goes into lock
(REFCLK compared to the
divided down VCO clock)
330
Maximum run length of serial
data input before out of lock is
declared
80
1000
UI
UI
No transitions on RSDP/N.
Sinusoidal input jitter.
Amplitude on SERDATI/P data
inputs from 12 kHz to 5 MHz.
OC-12/STS-12 Jitter Tolerance
0.4
* Noise on REFCLK should be less than 14 ps rms in a jitter frequency band from 12 kHz to 5 MHz.
20
September 16, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
