S3038
SONET/SDH/ATM OC-12 QUAD TRANSCEIVER
Table 7. Receiver Output Signals Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin #
Description
POUTA0
POUTA1
POUTA2
POUTA3
POUTA4
POUTA5
POUTA6
POUTA7
TTL
O
J1
J3
Channel A Receiver Data Outputs. Parallel data on this bus is
valid on the rising edge of POCLKAP.
J2
H1
H2
H3
F1
G2
FPA
TTL
O
F2
Frame Pulse. A High on this output indicates that valid data has
been detected and is present on the Parallel Data Output
POUTA[7:0].
POCLKAP
POCLKAN
TTL
TTL
O
O
K2
K1
Receive Data Clock. Parallel receive data, POUTA[7:0], are valid
on the rising edge of POCLKAP.
POUTB0
POUTB1
POUTB2
POUTB3
POUTB4
POUTB5
POUTB6
POUTB7
R1
P1
M3
N2
M2
N1
L2
Channel B Receiver Data Outputs. Parallel data on this bus is
valid on the rising edge of POCLKBP.
M1
FPB
TTL
O
L1
Frame Pulse. A High on this output indicates that valid data has
been detected and is present on the Parallel Data Output
POUTB[7:0].
POCLKBP
POCLKBN
TTL
TTL
O
O
U1
T1
Receive Data Clock. Parallel receive data, POUTB[7:0] are valid
on the rising edge of POCLKBP.
POUTC0
POUTC1
POUTC2
POUTC3
POUTC4
POUTC5
POUTC6
POUTC7
R7
R6
T5
U3
T4
R5
U2
T3
Channel C Receiver Data Outputs. Parallel data on this bus is
valid on the rising edge of POCLKCP.
FPC
TTL
TTL
O
O
R2
Frame Pulse. A High on this output indicates that valid data has
been detected and is present on the Parallel Data Output
POUTC[7:0].
POCLKCP
POCLKCN
U5
U4
Receive Data Clock. Parallel receive data, POUTC[7:0] are valid
on the rising edge of POCLKCP.
14
September 16, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
