S2066
QUAD GIGABIT ETHERNET TRANSCEIVER
Figure 8. S2066 Pinout (Top View)
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
COM_
DETB
RBC1B
RBC0B
DOUTB7 DOUTB6 DOUTB2 DOUTB0
COM_
RBC0A
RBC1A
DOUTA7
DOUTA5
DOUTA6
DOUTA4
DOUTA3
DOUTA2
DOUTA9
DOUTA0
DOUTA8
DOUTA1 TTLPWR TTLGND DIGGND DIGPWR
VDDA
1
2
COM_
DETA
DOUTC1 DOUTC9
DOUTB8 DOUTB4 DOUTB3 DOUTB1
TTLGND DIGGND
CMODE
DIGGND
VSSA
DIGPWR VSSSUB
DETC
DOUTC4 DOUTC0 DIGGND DOUTC8 TTLPWR DOUTB5 TTLGND DOUTB9
TTLGND DIGPWR
PWR
RXAP
GND
RXAN
VDD
PWR
VSS
3
TEST
MODE
RBC0C
RBC1C
DOUTC3 TTLGND TTLGND DIGGND TTLGND DIGPWR TTLPWR TTLGND TTLPWR TTLPWR DIGGND
4
DOUTC5 DOUTC2 TTLPWR
DOUTD9 DOUTC6 TTLGND
PWR
RXBN
VDD
GND
5
COM_
DETD
VSS
RXBP
VDDA
VSSSUB
RXCP
RXCN
GND
6
DOUTD1 DOUTD8 DOUTC7 TTLPWR
DOUTD2 DOUTD0 TTLGND TTLPWR
DOUTD5 DOUTD3 DOUTD4 DIGPWR
PWR
GND
VSSA
VSSA
PWR
VSS
7
VSSSUB
VDD
VDDA
8
PWR
9
RBC0D
DOUTD7
TBCA
RBC1D
DINA0
DINA4
DINA5
DINB0
DINB5
DINB8
DINC1
DOUTD6 DIGGND
PWR
GND
10
11
12
13
14
15
16
17
DINA1
DINA6
TBCB
DINB4
DINB7
DINB9
DINC4
DINA2
DINA7
DINB1
DINB6
TBCC
DINC3
DINC8
VSSA
RATE
CAP1
LPEN
GND
RXDP
PWR
RXDN
TMODE
VSS
VSS
CLKSEL
VSSSUB
CAP2
VDD
DINA3
DINA8
DINA9
DINB2
DINB3
VDDA
VSSSUB
VDD
DINC0
DINC2
DINC6
DINC9
DINC5
DINC7
DIND1
DIND3
TBCD
DIND0
DIND2
DIND7
DIND4
DIND5
DIND6
DIND8
TCLKO
DIGGND
DIND9
GND
GND
GND
GND
GND
GND
GND
PECL
PWR
RESET
PECLGND
TXBP
VSSA
PWR
TXAN
PECL
PWR
PECLGND
TXCP
TXDP
GND
GND
VDDA
TXAP
DIGPWR REFCLK
TXDN
TXCN
TXBN
18
October 13, 2000 / Revision C
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
