QUAD GIGABIT ETHERNET TRANSCEIVER
S2066
Table 10. S2066 Mode Control Signal Assignment and Description
Pin Name
Level
I/O
Pin #
Description
TESTMODE
TTL
I
E4
Test Mode Control. Keep Low for normal operation.
TMODE
CLKSEL
TTL
TTL
I
I
B13
C12
Transmit Mode Control. When TMODE is Low, REFCLK is used
to clock data on DINx[0:9] into the S2066. When TMODE is
High, TBCx is used to clock data into the S2066.
REFCLK Select Input. This signal configures the PLL for the
appropriate REFCLK frequency. When CLKSEL=0, the REFCLK
frequency should equal the parallel word rate. When
CLKSEL=1, the REFCLK frequency should be 1/2 the parallel
data rate.
REFCLK
RESET
TTL
TTL
I
I
H17
C15
Reference Clock is used for the transmit VCO and frequency
check for the clock recovered from the receiver serial data.
When Low, the S2066 is held in reset. The receiver PLL is forced
to lock to the REFCLK. The FIFOs are initialized on the rising edge
of RESET. When High, the S2066 operates normally.
RATE
TTL
I
D12
When Low, the S2066 operates with the serial output rate equal
to the VCO frequency. When High, the S2066 operates with the
VCO internally divided by 2 for all functions.
Note: All TTL inputs except REFCLK have internal pull-up networks.
15
October 13, 2000 / Revision C
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
