S2066
QUAD GIGABIT ETHERNET TRANSCEIVER
Table 5. Transmitter Input Signals Assignment and Description
Pin Name
Level
I/O
Pin #
Description
DINA9
TTL
I
U15
U14
P12
R12
T13
T12
U13
P11
R11
T11
Transmit Data for Channel A. Parallel data on this bus is clocked
in on the rising edge of TBCA or REFCLK. (See Table 2.)
DINA8
DINA7
DINA6
DINA5
DINA4
DINA3
DINA2
DINA1
DINA0
TBCA
TTL
TTL
I
I
U12
Transmit Byte Clock A. When TMODE is High, this signal is used
to clock Data on DINA[0:9] into the S2066. When TMODE is Low,
TBCA is ignored.
DINB9
DINB8
DINB7
DINB6
DINB5
DINB4
DINB3
DINB2
DINB1
DINB0
R16
T16
R15
P14
T15
R14
U17
U16
P13
T14
Transmit Data for Channel B. Parallel data on this bus is clocked in
on the rising edge of TBCB or REFCLK. (See Table 2.)
TBCB
TTL
TTL
I
I
R13
Transmit Byte Clock B. When TMODE is High, this signal is used
to clock Data on DINB[0:9] into the S2066. When TMODE is Low,
TBCB is ignored.
DINC9
DINC8
DINC7
DINC6
DINC5
DINC4
DINC3
DINC2
DINC1
DINC0
N17
P17
M15
N16
M14
R17
P16
N15
T17
N14
Transmit Data for Channel C. Parallel data on this bus is clocked in
on the rising edge of TBCC or REFCLK. (See Table 2.)
TBCC
TTL
I
P15
Transmit Byte Clock C. When TMODE is High, this signal is used
to clock Data on DINC[0:9] into the S2066. When TMODE is Low,
TBCC is ignored.
Note: All TTL inputs except REFCLK have internal pull-up networks.
10
October 13, 2000 / Revision C
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
