S2066
QUAD GIGABIT ETHERNET TRANSCEIVER
The TBC must be frequency locked to REFCLK, but
may have an arbitrary but fixed phase relationship.
Adjustment of internal timing of the S2066 is per-
formed during reset. Once synchronized, the S2066
can tolerate up to ±3ns of phase drift between TBC
and REFCLK.
serial data rate equals the VCO frequency. When
RATE is HIGH, the VCO frequency is divided by 2
before being provided to the rest of the chip. Thus
the S2066 can support Gigabit Ethernet and serial
backplane functions at both full and 1/2 the VCO
rate.
Figure 5 demonstrates the flexibility afforded by the
S2066. A low jitter reference is provided directly to
the S2066 at either 1/10 or 1/20 the serial data rate.
This insures minimum jitter in the synthesized clock
used for serial data transmission. A system clock
output at the parallel word rate, TCLKO, is derived
from the PLL and provided to the upstream circuit as
a system clock. This clock can be buffered as re-
quired without concern about added delay. There is
no phase requirement between TCLKO and the
TBCx clock, which is provided back to the S2066,
other than that they remain within ± 3ns of the phase
relationship established at reset .
Parallel-to-Serial Conversion
The 10-bit parallel data handled by the S2066 device
should be from a DC-balanced encoding scheme,
such as the 8B/10B transmission code, in which in-
formation to be transmitted is encoded, 8 bits at a
time, into a 10-bit transmission character and must
be compliant with IEEE 802.3z Gigabit Ethernet
specification.
The 8B/10B transmission code includes serial en-
coding and decoding rules, special characters, and
error control. Information is encoded, 8 bits at a time,
into a 10 bit transmission character. The characters
defined by this code ensure that short run lengths
and enough transitions are present in the serial bit
stream to make clock recovery possible at the re-
ceiver. The encoding also greatly increases the like-
lihood of detecting any single or multiple errors that
might occur during the transmission and reception of
data1.
The S2066 also supports the traditional REFCLK
clocking found in Gigabit Ethernet applications and
is illustrated in Figure 6.
Half Rate Operation
The S2066 supports full and 1/2 rate operation for all
modes of operation. When RATE is LOW, the S2066
Table 3 identifies the mapping of the 8B/10B charac-
ters to the data inputs of the S2066. The S2066 will
serialize the parallel data for each channel and will
transmit bit “a” or DIN[0] first.
Figure 6. GE DIN Clocking with REFCLK
125 MHz
Frequency Synthesizer (PLL)
REF
OSCILLATOR
1. A.X. Widner and P.A. Franaszek, "A Byte-Oriented DC Bal-
anced (0,4) 8B/10B Transmission Code," IBM Research Report
RC9391, May 1982.
REFCLK
TCLKO
PLL
DINx[0:9]
Table 3. Data to 8B/10B Alphabetic Representation
Data Byte
TBCx
DIN[0:9] or DOUT[0:9]
8B/10B alph. repr.
0
a
1
b
2
c
3
d
4
e
5
i
6
f
7
g
8
h
9
j
MAC
S2066
ASIC
6
October 13, 2000 / Revision C
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
