S2054
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
Table 2. S2054 Transmitter Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin # Description
TX9
TX8
TX7
TX6
TX5
TX4
TX3
TX2
TX1
TX0
LVTTL
I
11
10
9
Transmit data. Parallel data on this bus is clocked in on the
rising edge of REFCLK (TTL or PECL). TX0 is transmitted first.
8
7
6
5
4
3
2
REFCLKP
REFCLKN
LVPECL
LVTTL
I
I
22
23
Differential LVPECL. Reference clock and transmit byte clock. A
crystal-controlled reference clock for the PLL clock multiplier.
The frequency of REFCLKP/N is the bit rate divided by 10.
When TTL REFCLK (TREFCLK) is used, tie REFCLKP to VCC.
Let REFCLKN float. (Internally biased for AC coupling.)
TREFCLK
26
TTL reference clock and transmit byte clock, a crystal-controlled
reference clock for the PLL multiplier. The frequency of the
TREFCLK is the bit rate divided by 10. When PECL REFCLK is
used, let TREFCLK float or hold High (internal pull-up).
TX0P
TX0N
Diff.
O
O
60
59
Differential LVPECL outputs that send out the serial transmitter
data and drive 75Ω or 50Ω termination to Vcc–2V. TX0P is the
positive output, and TX0N is the negative output.
LVPECL
TX1P
TX1N
Diff.
LVPECL
63
62
Differential LVPECL outputs that send out the serial transmitter
data and drive 75Ω or 50Ω termination to Vcc–2V. TX1P is the
positive output, and TX1N is the negative output.
5
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
