®
DEVICE
SPECIFICATION
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
BiCMOS LVPECL CLOCK GENERATOR
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
GENERAL DESCRIPTION
S2054
S2054
FEATURES
• Functionally compliant with ANSI X3T11 Fibre
Channel physical and transmission protocol
standards and IEEE 802.3z Gigabit Ethernet
Applications
• Transmitter incorporates phase-locked loop
(PLL) providing clock synthesis from low-speed
differential LVPECL or LVTTL reference
• Receiver PLL configured for clock and data
recovery
• 1250 and 1062 Mb/s operation
• 10-bit parallel LVTTL compatible interface
• 1.1mW typical power dissipation
• +3.3V power supply
• Low-jitter serial LVPECL compatible interface
• Lock detect
• Dual serial inputs and outputs
• Local loopback
• Compact 10mm x 10mm 64 PQFP package
• Fibre Channel framing performed by receiver
• Continuous downstream clocking from receiver
• Low jitter LVPECL reference clock input option
The S2054 transmitter and receiver chip is designed
to perform high-speed serial data transmission over
fiber optic or coaxial cable interfaces conforming to
the requirements of the ANSI X3T11 Fibre Channel
specification and IEEE 802.3z Gigabit Ethernet. The
chip runs at 1250.0, and 1062.5 Mbit/s data rates
with associated 10-bit data word.
The S2054 is similar to the S2052. The S2054 pro-
vides dual transmit and receive serial I/O in addition
to an optional LVTTL or differential LVPECL refer-
ence clock input and high drive LVTTL outputs. The
dual transmit and receive serial I/O are useful for
backbone applications in which redundant optical or
electrical links are required. The differential LVPECL
reference clock provides the lowest transmitter output
jitter solution. The high drive LVTTL outputs allow
longer trace lengths or connectors to be used be-
tween the S2054 and the Media Access Controller.
The chip performs parallel-to-serial and serial-to-paral-
lel conversion and framing for block-encoded data. The
transmitter’s on-chip PLL synthesizes the high-speed
clock from a low-speed reference. The receiver’s on-
chip PLL synchronizes directly to incoming digital signal
to receive the data stream. The transmitter and re-
ceiver each support differential LVPECL-compatible I/
O for fiber optic component interfaces, to minimize
crosstalk and maximize data integrity. Local line
loopback mode is provided for system diagnostics. Dual
serial inputs and dual serial outputs facilitate redun-
dant design and provide maximum flexibility.
Figure 1 shows a typical configuration incorporating
the chip, which is compatible with AMCC’s S2036 Open
Fiber Control (OFC) device (for 1062 operation only).
APPLICATIONS
High-speed data communications
• Workstation
• Frame buffer
• Switched networks
• Data broadcast environments
• Proprietary extended backplanes
• RAID drives
• Mass storage devices
Figure 1. System Block Diagram
S2036
Open Fiber
Control
(OFC)
Gigabit
Ethernet
Controller
Optical
TX
Optical
RX
S2054
Optical
RX
Optical
TX
S2054
Gigabit
Ethernet
Controller
S2036
Open Fiber
Control
(OFC)
1
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
