S2054
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
Table 3. S2054 Receiver Pin Assignment and Descriptions
Pin Name
Level I/O
Pin # Description
RX9
RX8
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
LVTTL
O
34
35
36
38
39
40
41
43
44
45
Receive data outputs. Parallel data on this bus is valid on the
rising edge of RBC0 and RBC1. RX0 is the first bit received.
RBC1
RBC0
Diff.
O
I
30
31
Receive clock. Parallel data is valid on the rising edge of RBC0
and RBC1 (see timing diagram in Figure 8). After a sync word is
detected, the period of the current RBC1 and RBC0 is stretched
to align with the word boundary.
LVTTL
EN_CDET
LVTTL
24
Enable comma detect. When High, enables sync detection.
Detection of the 7-bit comma + character sync pattern, RX(0-9)
= (K28.5:0011111XXX), will enable the word boundary for the
data to follow. When Low, data is treated as unframed data.
RX0P
RX0N
Diff.
I
I
I
53
52
Primary Differential LVPECL received serial data inputs. RXP is
the positive input, and RXN is the negative input.
(Internally biased for AC coupling.)
LVPECL
RX1P
RX1N
Diff.
LVPECL
56
55
Secondary Differential LVPECL received serial data inputs. RXP
is the positive input, and RXN is the negative input.
(Internally biased for AC coupling.)
–LCK_REF
Static
27
Multi-level Static Lock to reference input. When Low, the RX
PLL will lock to the REFCLK input. When High, the RX PLL will
lock to the incoming data. When Open (not connected), the RX
will be held in reset.
COM_DET
LVTTL
O
47
Comma detect. Upon detection of a valid sync symbol, this
output goes high for one RBC1 period. When sync is active, the
sync character shall be present on the parallel data bus bits
RX0–RX9.
RCVSEL
EWRAP
LVTTL
Static
I
I
13
19
Receiver input select. When Low, RX0P-RX0N is selected as
the serial receiver input. When High, RX1P-RX1N is selected.
Wrap input. When High, selects the transmitter serial output
data to be routed to the receiver. When Low, the serial data is
selected by the RCVSEL input. TXP, TXN are static when
EWRAP is High.
6