S2054
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figure 4. A block diagram showing the basic chip
operation is shown in Figure 3.
S2054 OVERVIEW
The S2054 transmitter and receiver provide serializa-
tion and deserialization functions for block-encoded
data to implement a Fibre Channel interface. Opera-
tion of the S2054 is straightforward, as depicted in
Figure 2. The sequence of operations is as follows:
Loopback
Local loopback is supported by the chip, and pro-
vides a capability for performing offline testing of the
interface to ensure the integrity of the serial channel
before enabling the transmission medium. It also al-
lows for system diagnostics.
Transmitter
1. 10-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver
Figure 2. Interface Diagram
1. Clock and data recovery from serial input
2. Serial-to-parallel conversion
3. Frame detection
Parallel
Data Out
Parallel
Data In
4. 10-bit parallel output
RBC0/1
S2054
Transceiver
The 10-bit parallel data handled by the S2054 device
should be from a DC-balanced encoding scheme, such
as the 8B/10B transmission code, in which informa-
tion to be transmitted is encoded 8 bits at a time into
10-bit transmission characters1, and be compliant with
ANSI X3.230 FC-PH (Fibre Channel Physical and Sig-
naling Interface).
0
1
Serial
COM_DET
Data Out
0
Serial
Data In
1
REFCLK
RCVSEL
Figure 3. Functional Block Diagram
10
10
D
Q
TX [0:9]
Input
EWRAP
Latch
2
2
SHIFT
REGISTER
TX0P/N
TX1P/N
TESTEN
PLL CLOCK
MULTIPLIER
F
= F X 10
0
1
TREFCLK
REFCLKP/N
2
SHIFT
REGISTER
D
RX0P/N
2
PLL CLOCK
RECOVERY
RX1P/N
3:1
10
BITCLK
TP/N
D
Q
RX[0:9]
RCVSEL
EWRAP
-LCK_REF
COM_DET
DETECT
LOGIC
COM_DET
RBC1
CONTROL
LOGIC
EN_CDET
RBC0
1. A.X. Widmer and P.A. Franaszek, “A Byte-Oriented DC Balanced (0,4) 8B/10B Transmission Code,” IBM Research Report RC 9391,
May 1982.
2
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
