S2054
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
synchronous to the clock synthesis unit serial clock
into the serial output shift register. The shift register
is clocked by the internally generated bit clock which
is 10x the reference clock input frequency. D0 is trans-
mitted first as described in annex N and Tables 22
and 23 of FC-PH. Table 1 shows the mapping of the
parallel data to the 8B/10B codes. Two serial data
outputs are provided.
TRANSMITTER FUNCTIONAL
DESCRIPTION
The S2054 transmitter accepts parallel input data and
serializes it for transmission over fiber optic or coaxial
cable media. The chip is fully compatible with the ANSI
X3T11 Fibre Channel standard, and supports the Fi-
bre Channel and Gigabit Ethernet data rates of 1250
and 1062 Mbit/sec. (See Figure 3.)
Reference Clock Input
Data Input
The reference clock input must be supplied with ei-
ther a differential LVPECL (REFCLKP/N) or
single-ended LVTTL (TREFCLK) clock source with
100 PPM tolerance to assure that the transmitted data
meets the Fibre Channel frequency limits. The inter-
nal serial clock is frequency locked to the reference
clock (125.00 or 106.25 MHz).
Transmit data is provided to the S2054 as 10-bit wide
LVTTL. Data is clocked into the S2054 on the rising
edge of REFCLK.
Parallel/Serial Conversion
The parallel-to-serial converter takes in 10-bit wide
data from the input latch and converts it to a serial
data stream. Parallel data is latched into the transmitter
using the reference clock. The data is then clocked
Table 1. Data Mapping to 8b/10b Alphabetic Representation
Data Byte
TX[0:9] or
0
a
1
b
2
c
3
d
4
e
5
i
6
f
7
g
8
h
9
j
RX[0:9]
8b/10b alphabetic
representation
Figure 4. Functional Waveform (1250 and 1062.5 Mbit/sec)
INPUT TIMING
REFCLKP/N
TREFCLK
(Input)
PARALLEL
DATA BUS
(Input)
K28.5
K28.5
SERIAL DATA
K28.5
K28.5
OUTPUT TIMING
RBC0
(Output)
RBC1
(Output)
COM_DET
(Output)
PARALLEL
DATA BUS
(Output)
K28.5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
K28.5
3
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
