S2054
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
Table 4. S2054 Common Pin Assignment and Descriptions
Pin Name
Level I/O
Pin # Description
ECLVCC
TTLGND
+3.3V
GND
–
–
28, 20
Core Power Supply (+3.3V)
33, 32,
46
TTL Ground
TTLVCC
3.3V
3.3V
–
–
29, 37,
42
TTL Power Supply (3.3V)
PECL I/O Power Supply (3.3V)
ECLIOVCC
54, 58,
61, 64
ECLIOVEE
AVCC
GND
3.3V
GND
GND
–
–
–
–
1, 57
18, 50
15, 51
21, 25
PECL I/O Ground
Analog Power Supply (3.3V)
Analog Ground
AVEE
ECLVEE
Core Ground
GND
GND
–
–
–
I
14
12
16
These pins require connection to Ground.
NC
No Connection. This pin has no electrical connection.
TESTEN
LVTTL
When LOW, REFCLK replaces internal TX and RX bit clock to
facilitate factory testing. When High or allowed to float (no DC
connection), the TX PLL will lock to the REFCLK input and the
RX PLL will lock to receive data.
RESET
LVTTL
LVTTL
I
I
17
48
When LOW, the S2054 is held in reset. This pin should either be
allowed to float (no DC connection) or held High for normal
operation.
TEST20
Factory Test Mode. This pin should either be allowed to float (no
DC connection) or held High for normal operation.
7
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
