S2054
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
Lock Detect
RECEIVER FUNCTIONAL DESCRIPTION
The S2054 lock detect function monitors the state of
the receiver phase-locked loop (PLL) clock recovery
unit. The PLL will lock within 250 bit times after the
start of receiving serial data inputs. If the serial data
inputs have an instantaneous phase jump (from a se-
rial switch, for example) the PLL will not indicate an
out-of-lock state, but will recover the correct phase align-
ment within 50 to 250 bit times, depending on the input
eye opening. (See Fig. 13). If a run length of 80-160
bits is exceeded, or if the input data rate varies by
more than approximately 600 ppm compared to the
reference clock, the loop will be declared out of lock.
When lock is lost, the PLL will shift from the serial input
data to the reference clock, so that the downstream
clock will maintain the correct frequency.
The S2054 receiver is designed to implement the ANSI
X3T11 Fibre Channel specification and the IEEE 802.3z
Gigabit Ethernet receiver functions. A block diagram
showing the basic chip function is provided in Figure 3.
Two serial inputs are provided by the S2054. The
RCVSEL pin is used to select the active input. When-
ever a signal is present on the selected pin, the S2054
attempts to achieve synchronization on both bit and
transmission-word boundaries of the received encoded
bit stream. Received data from the incoming bit stream
is provided on the device’s parallel data outputs.
The S2054 accepts serial encoded data from a fiber
optic or coaxial cable interface. The serial input stream is
the result of the serialization of 8B/10B encoded data by
an FC compatible transmitter. Clock recovery is performed
on-chip, with the output data presented to the Fibre
Channel transmission layer as 10-bit parallel data.
In any transfer of PLL control from the serial data to the
reference clock, the RBC1/RBC0 output remains phase
continuous and glitch free, assuring the integrity of down-
stream clocking.
Serial/Parallel Conversion
Lock to Reference
Serial data is received on the RX[0:1]P/N pins. The
PLL clock recovery circuit will lock to the data stream
if the clock to be recovered is within ±100 PPM of the
internally generated bit rate clock. The recovered clock
is used to retime the input data stream. The data is
then clocked into the serial to parallel output registers
on the edge of RBC1. Data is clocked out on the
rising edge of RBC1 and RBC0. The parallel data out
is 10 bits wide. The word clock (RBC1) is synchro-
nized to the incoming data stream word boundary by
the detection of the Fibre Channel comma character
(0011111XXX, positive running disparity).
The S2054 can be forced to lock to the REFCLK by
holding the –LCK_REF signal Low. For normal opera-
tion, –LCK_REF can be left unconnected or held High.
OTHER OPERATING MODES
Loopback
When local loopback is enabled, serial data from the
transmitter is internally routed to the receiver, where
the clock is extracted and the data is deserialized.
The parallel data is then sent to the subsystem for
verification. The high speed serial outputs are dis-
abled during loopback. This loopback mode provides
the capability to perform offline testing of the inter-
face to guarantee the integrity of the serial channel
before enabling the transmission medium. It also al-
lows system diagnostics.
Framing
The S2054 provides COM_DET character recognition
and data word alignment of the LVTTL compatible out-
put data bus. In systems where the COM_DET function
is undesired, a LOW on the EN_CDET input disables
the COM_DET function and the data will be “un-framed”.
Operating Frequency Range
When framing is disabled by low EN_CDET, the S2054
simply achieves bit synchronization within 250 bit times
and begins to deliver parallel output data words whenever
it has received full transmission words. No attempt is made
to synchronize on any particular incoming character.
The S2054 is optimized for operation at 1250 and
1062 Mbit/s. Operation at other rates is possible if the
rate falls between the nominal rates. REFCLK must
be selected to be within 100 ppm of the desired byte
or word clock rate.
The COM_DET output signal will go high whenever a
K28.5 character (positive disparity) is present on the
parallel data outputs and EN_CDET is High. If
EN_CDET is Low, comma characters will not be re-
ported. The COM_DET output signal will be low at all
other times.
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
