Revision J – April 7, 2006
S2004 – Quad Serial Backplane Device
Data Sheet
Figure 12. S2004 Pinout (Bottom View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
u
DIG-
PWR
DIG-
GND
TTLG
ND
TTLP
WR
DOUT
A1
DOUT
A4
DOUT
A7
DOUT
B0
DOUT
B2
DOUT
B6
DOUT
B7
VDDA
RXAP
RXAN
VSS
ERRA
RCAN
RCAP
ERRB
EOFB
RCBN
ERRC
RCBP
1
2
DIG-
PWR
CMOD
E
DIG-
GND
TTLG
ND
DOUT
A0
DOUT
A3
DOUT
A5
DOUT
B1
DOUT
B3
DOUT
B4
KFLA
GB
DOUT
C1
EOFA
EOFC
DIG-
GND
DIG-
PWR
TTLG
ND
KFL-
AGA
DOUT
A2
DOUT
A6
TTLG
ND
DOUT
B5
TTLP
WR
KFLA
GC
DIG-
GND
DOUT
C0
DOUT
C4
TRS
VDD
GND
3
CH_L
OCK
DIG-
GND
TTLP
WR
TTLP
WR
TTLG
ND
TTLP
WR
DIG-
PWR
TTLG
ND
DIG-
GND
TTLG
ND
TTLG
ND
DOUT
C3
VSSA
NC
SYNC
RCCN
RCCP
EOFD
4
VSS-
SUB
TTLP
WR
DOUT
C2
DOUT
C5
RXBP
VDDA
RXBN
VDD
5
TTLG
ND
DOUT
C6
VDD
NC
VSS
NC
ERRD
6
VSS-
SUB
TTLP
WR
DOUT
C7
KFLA
GD
DOUT
D1
VSSA
VSSA
NC
7
VSS-
SUB
TTLP
WR
TTLG
ND
DOUT
D0
DOUT
D2
RXCP
RXCN
TMS
VDDA
NC
8
DIG-
PWR
DOUT
D4
DOUT
D3
DOUT
D5
VDD
TDI
9
DIG-
GND
DOUT
D6
VSS
TCK
NC
RCDP
DINA0
DINA4
DINA5
DINB0
DINB5
RCDN
10
11
12
13
14
15
16
17
DOUT
D7
VSS
RXDP
RXDN
VSSA
RATE
CAP1
DINA2
DINA7
DINB1
DINB6
DINA1
DINA6
CLK-
SEL
TCLK
A
VDD
TMOD
E
VSS-
SUB
TCLK
B
VDDA
DINA3
VSS-
SUB
LPEN
A
LPEN
B
LPEN
D
TCLK
O
TCLK
D
KGEN
A
VSS
VSSA
PWR
TXAN
CAP2
NC
NC
NC
DIND4
DIND5
DIND6
DINC5
DINC7
DIND1
DIND3
DINC0
DINC2
DINC6
DNC
DINB4
DINB7
DNB
RESE
T
PECL
PWR
PECL
PWR
LPEN
C
DIG-
GND
TCLK
C
VDD
VDDA
TXAP
TC0
DIND0
DIND2
DIND7
DNA
PECL
GND
PECL
PWR
PECL
PWR
PECL
GND
KGEN
B
NC
TXCN
TXDP
DND
DINC3
DINB2
DINB3
REF-
CLK
DIG-
PWR
KGEN
D
KGEN
C
TXBP
TXBN
TXCP
TXDN
DINC4
DINC1
Note: NC used as Test Pins. Do Not Connect.
30
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