Revision J – April 7, 2006
S2004 – Quad Serial Backplane Device
Data Sheet
Table 15. Receiver Control Signals
Pin Name Level I/O Pin #
Description
LPENA
LPENB
LPENC
LPEND
TTL
TTL
I
I
D14
G14
G15
H14
Loopback Enable. When Low, input source is the high speed serial input for each chan-
nel. When High, the serial output for each channel is looped back to its input.
CMODE
C2
Clock Mode Control. When Low, the parallel output clocks (RCxP/N) rate is equal to 1/2
the data rate. When High, the parallel output clocks (RCxP/N) rate is equal to the data
rate.
Note: All TTL inputs except REFCLK have internal pull-up networks.
Table 16. Power and Ground Signals
Pin Name
VDDA
Qty.
Pin #
Description
5
A1, A6, A13, A16, C8
Analog Power (VDD) low noise.
VSSA
VDD
5
6
B7, B8, B15, C4, D11
Analog Ground (VSS).
A12, A15, B4, B6, C6, D9
Power for High Speed Circuitry (VDD).
Ground for High Speed Circuitry (VSS).
VSS
VSSSUB
10
A4, A7, A11, A14, B10, B14, C13,
D5, D6, D8
PECLPWR
PECLGND
DIGPWR
DIGGND
TTLPWR
TTLGND
4
2
D15, E15, E16, G16
PECL Power (VDD
PECL Ground (VSS
Core Circuitry Power (VDD
Core Circuitry Ground (VSS
Power for TTL I/O (VDD
)
C16, H16
)
6
B1, B2, E3, J17, L4, P9
C1, C3, D2, F4, J15, N4, P10, R3
E1, G4, H4, K4, N3, P5, P7, P8
)
8
)
8
)
10
D1, E2, F3, J4, L3, M4 P4, P6, R4,
R8
Ground for TTL I/O (VSS)
PWR
GND
1
1
2
B16
D3
Power
Ground
CAP1
CAP2
D13
C14
Pins for external loop filter capacitor
NC
10
B9, C5, C7, C9, C11, D7, D16, E14,
F14, F15
Not Connected. Used as Test Pins. Do Not Connect.
28
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