Revision J – April 7, 2006
S2004 – Quad Serial Backplane Device
Data Sheet
Table 17. JTAG Test Signals
Pin Name
Level
I/O
Pin #
Description
TMS
TTL
I
A10
Test Mode Select. Enables JTAG testing of device.
TCK
TDI
TTL
TTL
TTL
I
I
C10
D10
H15
Test Clock. JTAG test clock.
Test Data In. JTAG data input.
TDO
O
TRISTAT
E
Test Data Out. JTAG data output. Can be high impedance under JTAG control-
ler command.
TRS
TTL
I
B3
Test Reset. Resets JTAG test state machine.
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