Revision J – April 7, 2006
S2004 – Quad Serial Backplane Device
Data Sheet
Table 11. Transmitter Input Pin Assignment and Descriptions (Continued)
Pin Name
Level
I/O
Pin #
Description
TCLKD
TTL
I
L14
Transmit Data Clock D. When TMODE is High, this signal is used to clock Data on
DIND[0:7], KGEND, and DND into the S2004. When TMODE is Low, TCLKD is
ignored. In Channel Lock Mode, HIGH, TCLKD (Low) is used to reset the Chan-
nel=CH_LOCK Lock state machine.
SYNC
TTL
I
D4
When High, (See Table 2) used to generate a special sequence of K28.5 characters.
See earlier text.
Table 12. Transmitter Output Signals
Pin Name
Level
I/O
Pin #
Description
High speed serial outputs for Channel A.
TXAP
TXAN
Diff. LVPECL
O
A17
B17
TXBP
TXBN
Diff. LVPECL
Diff. LVPECL
Diff. LVPECL
TTL
O
O
O
O
C17
D17
High speed serial outputs for Channel B.
High speed serial outputs for Channel C.
High speed serial outputs for Channel D.
TXCP
TXCN
E17
F16
TXDP
TXDN
F17
G17
TCLKO
J14
TTL Output Clock at the Parallel data rate. This clock is provided for use by
up-stream circuitry.
Table 13. Mode Control Signals
Pin Name
Level
I/O
Pin #
Description
CH_LOCK
TTL
I
E4
Parallel Input Mode Control. Channel Lock High locks all four channels together.
(See Table 1.)
TMODE
TTL
I
B13
Transmit Mode Control. Controls the source of the clock used to input and output
data to and from the S2004. When TMODE is Low, REFCLK is used to clock data on
DINx[0:7], DNx, SYNC, and KGENx into the S2004. TCLKA is used to clock parallel
data DOUTx[0:7], EOFx, ERRx, and KFLAG out of the device. When TMODE is
High:
In Channel Lock Mode, TCLKA clocks data into the S2004 for all four channels and
the output clock is derived from the receiver A CRU. For Independent Mode, each
channel is clocked by its respective TCLKx. The output clocks are derived from the
receivers' CRUs.
CLKSEL
REFCLK
RESET
TTL
TTL
TTL
I
I
I
C12
H17
C15
REFCLK Select Input. This signal configures the PLL for the appropriate REFCLK
frequency. When CLKSEL = 0, the REFCLK frequency equals the parallel word rate.
When CLKSEL = 1, the REFCLK frequency is 1/2 the parallel data rate.
Reference Clock is used for the transmit VCO and frequency check for the clock
recovered from the receiver serial data. Also used to clock parallel data into the
device when in REFCLK mode.
When Low, the S2004 is held in reset. The receiver PLL is forced to lock to the REF-
CLK. The FIFOs are initialized on the rising edge of RESET. When High, the S2004
operates normally.
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