Revision 3.03 – May 25, 2007
S1220 – SONET/SDH/ATM Quad OC-3/12
with Clock Data Recovery (CDR)
Advance Data Sheet
Table 12. MDIO Control Bits Functionality
Bit Name
Function
SDPOL
Defines Signal Detect polarity
Setting this bit Low will set the SD inputs as active High. Setting this bit High will set the SD inputs as
active Low. This input can be accessed through the MDIO bus register in MII mode and via SDPOL pin in
Non-MII Mode.
OUTMODE
Defines Serial output mode when SERDATOP/N and SERCLKOP/N are disabled. If SERDATOP/N or
SERCLKOP/N are not used, then these outputs can be forced to zero or to a high impedance state. The
default value for SERDATOP/N or SERCLKOP/N is high Z. Advantage for the board configuration. Used in
conjunction with SERCLKOOFF and TSDEN [3:0].
1->logic 0 state (Low level for LVDS or LVPECL) and 0->High Z
CLVDSPECLB
XLVDSPECLB
XACEN
CSU Transmit Serial Clock Output Mode (TSCLKP/N).
1 - LVDS Mode
0 - LVPECL Mode
Serial Clock and Data Output (SERCLKOP/N & SERDATOP/N) Mode.
1 - LVDS Mode
0 - LVPECL Mode
Serial Data Input Coupling Mode. Selects the type of coupling for the SERDATIP/N input.
1 - Default. AC coupling mode.
0 - DC coupling mode.
CDCBIAS
Common Mode DC Bias. Active High. Enables Common mode DC bias for DC LVPECL connection with-
out external resistors for CSU (REFCLK) inputs. This function is controlled by the CDCBIAS I/O pin when
not in MII Mode.
1 - Enabled.
0 - Default. Disabled.
XDCBIAS
Serial Input DC Bias Setting. Active High. When active, it enables common mode DC bias for DC LVPECL
connection without external resistors for Serial Data inputs (SERDATIP/N). This function is controlled by
the DCBIAS I/O pin when not in MII Mode.
1 - Active.
0 - Default. Inactive.
REFSEL[1:0]
RATESEL
Reference Clock Selection. This function is controlled by the REFSEL I/O pins when not in MII Mode
REFSEL[1:0] = 1x selects 155.52 MHz Refclk.
REFSEL[1:0] = 01 selects 77.76 MHz Refclk.
Default. REFSEL[1:0] = 00 selects 19.44 MHz Refclk.
Rate Select. This bit selects the desired operating rate CSU (TSCLKP/N). CSU rate is OC-12 if any of the
channels is in OC-12 rate.
1 - Default. OC-12.
0 - OC-3.
RATESEL[3:0]
Rate Select. This bit selects the desired operating rate of each channel [3:0].
1 - Default. OC-12.
0 - OC-3.
LOCKDET[3:0]
(status output)
Lock Detect Indicator. Active High. This Read Only register displays the current lock condition of the CDR.
1 - CDR is in lock.
0 - CDR is out of lock.
TXLOCK
Lock Detect Indicator. Active High. This Read Only register displays the current lock condition of the trans-
mit CSU. In MII mode direction control bit is required from the register for the output. In Non-MII mode this
is an input for REFSEL1.
1 - CSU is in lock.
0 - CSU is out of lock.
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