QT2022/32 - Data Sheet: DS3051
6.2.5 VCXO PLL Implementation Recommendations
VCXO PLL Pin Settings
Recommended pin settings for each potential application of the VCXO PLL are listed in Table 6 on page 34.
Table 6: VCXO PLL Control Pin Settings
Implementation
QT2032 Pin Settings
No
155.52
x
1
1
0
0
0
0
0
0
x
x
0
0
0
0
1
1
0
1
0
0
1
1
0
1
x
x
0
1
0
1
0
1
No
622.08
x
Yes
Yes
Yes
Yes
Yes
Yes
155.52
155.52
622.08
155.52
622.08
155.52
622.08
155.52
622.08
622.08
No source 1
No source 1
1.
If no SREFCLK is implemented, and 20ppm operation for SONET applications is required, then the VCXO will likely need to be tem-
perature-compensated.
6.2.6 VCXO Usage for QT2032 in LAN Mode
Usage of an external VCXO is not supported in LAN mode. When a VCXO is implemented and the chip is switched
to LAN mode, the VCXO must be disabled by setting pin VCXOB=1. If external control to the VXCOB pin is not
available, the polarity of the pin logic can be inverted. This is accomplished by setting MDIO register bit
1.D003h.9=1.
Control of the operating mode (WAN or LAN) is described in Section 8.3.1 on page 59.
34
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