QT2022/32 - Data Sheet: DS3051
Rx Pseudo-Random Block Counter
3.CC05h
Rx Pseudo-Random Block Error counter
3.CC06h
Bit
15:0
Received Pseudo-Random Block counter, RO
Non-rollover
Received Pseudo-Random Block Error counter, RO
Non-rollover
latched on read
cleared on read of 3.CC06h
latched on read of 3.CC05h
cleared on read
RMDIO
Control
3.CC08h
RMDIO Device Address
Control
RMDIO Register Address
Control
Bit
3.CC09h
3.CC0Ah
0
PHY RMDIO feature TX enable, RW
0 = disabled, default
1 = enabled
MDIO Device Address, RW
5’h01 = PMA/PMD (default)
5’h02 = WIS
MDIO Register Address, RW
Default value is 16’h0000
5’h03 = PCS
5’h04 = XGXS
other = Unsupported device
address
1
2
3
PHY RMDIO feature RX enable, RW
0 = disabled
1 = enabled, default
PHY RMDIO Remote Read Request, RW
1= Remote Read Requested
0= No Action (default)
PHY RMDIO Remote Write Request 1 2, RW
1= Remote Write Requested
0= No Action (default)
4
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
5
6
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
7
8
9
10
11
12
13
14
15
1. RMDIO write request has a lower priority than RMDIO read request. If both are activated simultaneously, the read request will be sent
first.
2. The RMDIO write feature is password protected to prevent accidental writes. To enable RMDIO writes, the correct password must be
written to Register 3.CC0Fh. Please contact AMCC for further information.
Revision 5.11
AppliedMicro - Confidential & Proprietary
173
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
