Revision 1.23 - Sept 26, 2006
Data Sheet
PowerPC 440SP Embedded Processor
Table 6. Signal Functional Description (Sheet 3 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
DDR SDRAM Interface
2.5(1.8)V
DDR SDRAM
BA0:2
Bank Address supporting up to eight internal banks.
Selects up to two external DDR SDRAM banks.
Column Address Strobe.
O
O
O
O
O
2.5(1.8)V
DDR SDRAM
BankSel0:1
CAS
2.5(1.8)V
DDR SDRAM
2.5(1.8)V
DDR SDRAM
ClkEn0:1
DM0:8
Clock Enable. One for each external bank.
Memory write data byte lane masks. MEMDM8 is the
byte lane mask for the ECC byte lane.
2.5(1.8)V
DDR SDRAM
2.5(1.8)V
DDR SDRAM
DIFF
DQS0:8
DQS0:8
Byte lane data strobe. DQS8 is the data strobe for the
ECC byte lane. These signals are differential pairs.
I/O
2.5(1.8)V
DDR SDRAM
ECC0:7
ECC check bits 0:7.
I/O
O
Memory address bus.
2.5(1.8)V
DDR SDRAM
MemAddr14:00
Note:MemAddr14 is the most significant bit (msb).
2.5(1.8)V
DDR SDRAM
DIFF
MemClkOut0:1
MemClkOut0:1
Subsystem clocks. These signals are differential pairs.
O
Memory data bus.
2.5(1.8)V
DDR SDRAM
MemData63:00
I/O
Note:MemData63 is the most significant bit (msb).
2.5(1.8)V
DDR SDRAM
MemDCFdbkD
MemDCFdbkR
MemODT0:1
Feedback driver, for I/O timing measurements.
O
I
Feedback receiver. Connect externally to
MemDCFdbkD.
2.5(1.8)V
DDR SDRAM
2.5(1.8)V
DDR SDRAM
Memory on-die termination control.
O
2.5(1.8)V
DDR SDRAM Volt Ref
Rcv
Memory reference voltage (SVREF) input.
MemVRef0
MemVRef1
I
I
2.5(1.8)V
DDR SDRAM Volt Ref
Sup
Memory reference voltage (SVREF) supplemental input.
2.5(1.8)V
DDR SDRAM
RAS
WE
Row Address Strobe.
Write Enable.
O
O
2.5(1.8)V
DDR SDRAM
58
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
