Revision 1.23 - Sept 26, 2006
Data Sheet
PowerPC 440SP Embedded Processor
Table 6. Signal Functional Description (Sheet 5 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
1, 4
UART Peripheral Interface
Serial clock input that provides an alternative to the
internally generated serial clock. Used in cases where
the allowable internally generated clock rates are not
satisfactory.
UARTSerClk
I
3.3V LVTTL
UART0_Rx
UART0 Receive data.
I
O
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
1, 4
4
UART0_Tx
UART0 Transmit data.
UART0_DCD
UART0_DSR
UART0_CTS
UART0_DTR
UART0_RTS
UART0 Data Carrier Detect.
UART0 Data Set Ready.
UART0 Clear To Send.
UART0 Data Terminal Ready.
UART0 Request To Send.
6
I
6
I
1, 4
4
O
O
4
3.3V LVTTL
w/pull-up
UART0_RI
UART0 Ring Indicator.
I
1, 4
UART1_Rx
UART1_Tx
UART1 Receive data.
UART1 Transmit data.
I
3.3V LVTTL
3.3V LVTTL
1, 4
1, 4
O
UART1 Data Set Ready or Clear To Send. The choice is
determined by a DCR register bit setting.
UART1_DSR/CTS
UART1_DTR/RTS
I
3.3V LVTTL
3.3V LVTTL
1, 4
1, 4
UART1 Request To Send or Data Terminal Ready. The
choice is determined by a DCR register bit setting.
O
UART2_Rx
UART2_Tx
IIC Peripheral Interface
IIC0SClk
UART2 Receive data.
UART2 Transmit data.
I
3.3V LVTTL
3.3V LVTTL
1, 4
1, 4
O
IIC0 Serial Clock.
IIC0 Serial Data.
IIC1 Serial Clock.
IIC1 Serial Data.
I/O
I/O
I/O
I/O
3.3V IIC
3.3V IIC
3.3V IIC
3.3V IIC
1, 2
1, 2
1, 2
1, 2
IIC0SDA
IIC1SClk
IIC1SDA
Interrupts Interface
IRQ0:5
External interrupt Requests 0 through 5.
I
3.3V LVTTL
1, 5
60
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
