欢迎访问ic37.com |
会员登录 免费注册
发布采购

PPC440SP-AFC667C 参数 Datasheet PDF下载

PPC440SP-AFC667C图片预览
型号: PPC440SP-AFC667C
PDF下载: 下载PDF文件 查看货源
内容描述: 的PowerPC 440SP嵌入式处理器 [PowerPC 440SP Embedded Processor]
分类和应用: PC
文件页数/大小: 85 页 / 1264 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
 浏览型号PPC440SP-AFC667C的Datasheet PDF文件第52页浏览型号PPC440SP-AFC667C的Datasheet PDF文件第53页浏览型号PPC440SP-AFC667C的Datasheet PDF文件第54页浏览型号PPC440SP-AFC667C的Datasheet PDF文件第55页浏览型号PPC440SP-AFC667C的Datasheet PDF文件第57页浏览型号PPC440SP-AFC667C的Datasheet PDF文件第58页浏览型号PPC440SP-AFC667C的Datasheet PDF文件第59页浏览型号PPC440SP-AFC667C的Datasheet PDF文件第60页  
Revision 1.23 - Sept 26, 2006  
Data Sheet  
PowerPC 440SP Embedded Processor  
Table 6. Signal Functional Description (Sheet 1 of 7)  
Notes:  
1. Receiver input has hysteresis  
2. Must pull up (recommended value is 3kΩ to 3.3V)  
3. Must pull down (recommended value is 1kΩ)  
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)  
5. If not used, must pull down (recommended value is 1kΩ)  
6. Strapping input during reset; pull-up or pull-down required  
Signal Name  
Description  
I/O  
Type  
Notes  
PCI-X0:2 Interfaces  
Ack64 or ECC1.  
Normally used as Ack64 indicating that the target can  
transfer data using 64 bits.  
3.3V PCI or  
PCIX0:1Ack64/PCIX0:1ECC1  
I/O  
4
1.5V PCI for mode 2  
or  
Used as ECC1 for PCI-X mode 2.  
PCIX0:1AD63:00  
PCIX2AD31:00  
Address/Data bus (bidirectional) for PCI-X0 and PCI-X1.  
Address/Data bus (bidirectional) for PCI-X 2.  
3.3V PCI or  
I/O  
I/O  
1.5V PCI for mode 2  
PCI-X Byte Enables for PCI-X0 and PCI-X1.  
PCI-X Byte Enables for PCI-X2.  
PCIX0:1BE7:0  
PCIX2BE3:0  
3.3V PCI or  
1.5V PCI for mode 2  
PCIX0:1CalG0:1  
PCIX2CalG0  
External calibration resistor pads (G) for PCI-X0:2 (one  
pad for each 32-bit bus group).  
I
I
na  
na  
PCIX0:1CalR0:1  
PCIX2CalR0  
External calibration resistor pads (R) for PCIX0:2 (one  
pad for each 32-bit bus group).  
Capable of PCI-X operation.  
This analog input is sampled to configure PCI and  
determine the state of the PCIX0:2VC output signal:  
0.00VDD (0.0V) = Conventional PCI & PCIX0:2VC = 0  
PCIX0:2Cap  
I
na  
0.49VDD (1.6V) = PCI-X DDR 266 Mode 2 &  
PCIX0:2VC = 1  
0.75VDD (2.5V) = PCI-X 66 & PCIX0:2VC = 0  
1.00VDD (3.3V) = PCI-X 133 & PCIX0:2VC = 0  
Provides timing to the PCI interface for PCI transactions.  
Note:If the PCI-X interface is not being used, drive this  
pin with a 3.3V clock signal at a frequency  
between 1 and 66MHz  
PCIX0:2Clk  
I
3.3V PCI  
3.3V PCI  
Indicates the driving device has decoded its address as  
the target of the current access.  
PCIX0:2DevSel  
I/O  
4
ECC check bits 5–2. All ECC bits are valid only for PCIX  
DDR mode 2.  
PCIX0:2ECC5:2  
PCIX2ECC1  
PCIX2ECC6  
3.3V PCI or  
Note:See PCIX0:2Par for ECC0.  
See PCIX0:1Ack64 for ECC1.  
See PCIX0:1Req64 for ECC6.  
See PCIX0:1Par64 for ECC7.  
I/O  
1.5V PCI for mode 2  
Driven by the current master to indicate beginning and  
duration of an access.  
PCIX0:2Frame  
I/O  
I/O  
3.3V PCI  
3.3V PCI  
4
4
5
Indicates that the specified agent is granted access to  
the bus. When using an external PCI/PCI-X arbiter,  
connect the external arbiter's Grant line to this signal.  
PCIX0:2Gnt0:1  
PCIX0:1Gnt2:3  
Used as a chip select during configuration read and  
write transactions.  
PCIX0:2IDSel  
PCIX0:2INTA  
PCIX0:2IRDY  
I
3.3V PCI  
3.3V PCI  
3.3V PCI  
Level sensitive PCI interrupt.  
O
Indicates initiating agent’s ability to complete the current  
data phase of the transaction.  
I/O  
4
56  
AMCC Proprietary  
 复制成功!