Revision 1.23 - Sept 26, 2006
Data Sheet
PowerPC 440SP Embedded Processor
Table 6. Signal Functional Description (Sheet 6 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
System Interface
Description
I/O
Type
Notes
1, 4
Halt
Halt from external debugger.
I
3.3V LVTTL
3.3V LVTTL
General purpose I/O 0 through 17. To access these
functions, software must set DCR register bits.
GPIO00:17
I/O
General purpose I/O 18 through 29. To access these
functions, software must set DCR register bits.
GPIO18:29
GPIO30:31
I/O
I/O
3.3V PCI
General purpose I/O 30 through 31. To access these
functions, software must set DCR register bits.
3.3V LVTTL
SysClk
Main system clock input.
Set to 1 when a machine check is generated.
Not used.
I
O
I
3.3V LVTTL
3.3V LVTTL
na
SysErr
SysPartSel
3
Main system reset. External logic can drive this
bidirectional pin low (minimum of 16 cycles) to initiate a
system reset. A system reset can also be initiated by
software.
SysReset
I
3.3V LVTTL
1, 2
1, 2
HISRRst
ExtReset
Hardware initiated self-refresh and system reset.
I
3.3V LVTTL
3.3V LVTTL
External Reset. During the PPC440SP’s reset phase,
this signal is at down level.
O
TestEn
TmrClk
JTAG Interface
TCK
Test Enable.
I
I
3.3V LVTTL
3.3V LVTTL
3
Processor timer external input clock.
Test Clock.
I
I
3.3V LVTTL
3.3V LVTTL w/pull-down
3.3V LVTTL
1
4
TDI
Test Data In.
TDO
Test Data Out.
Test Mode Select.
O
I
TMS
3.3V LVTTL with pull-up
1
5
Test Reset. During chip power-up, this signal must be
low from the start of VDD ramp-up until at least 16
SysClk cycles after VDD is stable in order to initialize the
JTAG controller.
TRST
I
3.3V LVTTL with pull-up
Trace Interface
TrcClk
Trace data capture clock, runs at 1/4 the frequency of
the processor.
O
O
O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
TrcBS0:2
Trace branch execution status.
Trace Execution Status is presented every fourth
processor clock cycle.
TrcES0:4
Additional information on trace execution and branch
status.
TrcTS0:6
O
3.3V LVTTL
AMCC Proprietary
61
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
