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PPC440GP-3RC400C 参数 Datasheet PDF下载

PPC440GP-3RC400C图片预览
型号: PPC440GP-3RC400C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Power PC 440GP嵌入式处理器 [Power PC 440GP Embedded Processor]
分类和应用: 微控制器和处理器外围集成电路微处理器PC时钟
文件页数/大小: 83 页 / 1393 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.07 – October 4, 2007  
440GP – Power PC 440GP Embedded Processor  
Data Sheet  
Signal Functional Description (Sheet 5 of 7)  
Notes:  
1. Receiver input has hysteresis  
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)  
3. Must pull down (recommended value is 1kΩ)  
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)  
5. If not used, must pull down (recommended value is 1kΩ)  
6. Strapping input during reset; pull-up or pull-down required  
Signal Name  
UART1_RTS/DTR  
Description  
I/O  
Type  
Notes  
UART1 Request To Send or Data Terminal Ready. The choice is  
determined by a DCR register bit setting.  
5V tolerant  
3.3V LVTTL  
I/O  
1, 4  
IIC Peripheral Interface  
5V tolerant  
IIC0SClk  
IIC0 Serial Clock.  
IIC0 Serial Data.  
IIC1 Serial Clock.  
IIC1 Serial Data.  
I/O  
I/O  
I/O  
I/O  
1, 2  
1, 2  
1, 2  
1, 2  
3.3V LVTTL  
5V tolerant  
3.3V LVTTL  
IIC0SDA  
IIC1SClk  
5V tolerant  
3.3V LVTTL  
5V tolerant  
3.3V LVTTL  
IIC1SDA  
Interrupts Interface  
IRQ00:10  
5V tolerant  
External interrupt Requests 0 through 10.  
External interrupt Requests 11 through 12.  
I
I
1, 5  
3.3V LVTTL  
IRQ11:12  
3.3V PCI  
JTAG Interface  
3.3V CMOS  
w/pull-up  
TCK  
Test Clock.  
I
1
4
3.3V CMOS  
w/pull-up  
TDI  
Test Data In.  
I
O
I
TDO  
TMS  
Test Data Out.  
Test Mode Select.  
3.3V LVTTL  
3.3V CMOS  
w/pull-up  
1
5
Test Reset. During chip power-up, this signal must be low from the  
start of VDD ramp-up until at least 16 SysClk cycles after VDD is  
stable in order to initialize the JTAG controller.  
3.3V CMOS  
w/pull-up  
TRST  
I
52  
AMCC  
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