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PPC440GP-3RC400C 参数 Datasheet PDF下载

PPC440GP-3RC400C图片预览
型号: PPC440GP-3RC400C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Power PC 440GP嵌入式处理器 [Power PC 440GP Embedded Processor]
分类和应用: 微控制器和处理器外围集成电路微处理器PC时钟
文件页数/大小: 83 页 / 1393 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.07 – October 4, 2007  
440GP – Power PC 440GP Embedded Processor  
Data Sheet  
Signal Functional Description (Sheet 1 of 7)  
Notes:  
1. Receiver input has hysteresis  
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)  
3. Must pull down (recommended value is 1kΩ)  
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)  
5. If not used, must pull down (recommended value is 1kΩ)  
6. Strapping input during reset; pull-up or pull-down required  
Signal Name  
PCI-X Interface  
Description  
I/O  
Type  
Notes  
PCIXAD00:63  
Address/Data bus (bidirectional).  
I/O  
I/O  
3.3V PCI  
3.3V PCI  
PCIXC0:7[BE0:7]  
PCI-X Command[Byte Enables].  
Capable of PCI-X operation.  
5V tolerant  
3.3V LVTTL  
PCIXCap  
I
5
PCIX133Cap  
PCI-X devices are 133 MHz capable.  
O
3.3V PCI  
3.3V PCI  
Provides timing to the PCI interface for PCI transactions.  
PCIXClk  
I
Note:If the PCI-X interface is not being used, drive this pin with a  
3.3V clock signal at a frequency between 1 and 66MHz  
Indicates the driving device has decoded its address as the target  
of the current access.  
PCIXDevSel  
PCIXFrame  
I/O  
I/O  
3.3V PCI  
3.3V PCI  
4
4
Driven by the current master to indicate beginning and duration of  
an access.  
PCIXGnt0  
PCIXGnt1  
PCIXGnt2:5  
Indicates that the specified agent is granted access to the bus.  
Indicates that the specified agent is granted access to the bus.  
Indicates that the specified agent is granted access to the bus.  
I/O  
I/O  
O
3.3V PCI  
3.3V PCI  
3.3V PCI  
4
4
Used as a chip select during configuration read and write  
transactions.  
PCIXIDSel  
PCIXINT  
I
3.3V PCI  
3.3V PCI  
3.3V PCI  
5
Level sensitive PCI interrupt.  
O
Indicates initiating agent’s ability to complete the current data  
phase of the transaction.  
PCIXIRDY  
I/O  
4
5
5V tolerant  
3.3V LVTTL  
PCIXM66En  
Capable of 66MHz operation.  
I
PCIXParHigh  
PCIXParLow  
Even parity across PCIAD32:63 and PCIXC0:3[BE4:7].  
Even parity across PCIAD0:31 and PCIXC0:3[BE0:3].  
I/O  
I/O  
3.3V PCI  
3.3V PCI  
Reports data parity errors during all PCI transactions except a  
Special Cycle.  
PCIXPErr  
I/O  
I/O  
I
3.3V PCI  
3.3V PCI  
3.3V PCI  
4
4
4
An indication to the PCI-X arbiter that the specified agent wishes  
to use the bus.  
PCIXReq0  
PCIXReq1:5  
An indication to the PCI-X arbiter that the specified agent wishes  
to use the bus.  
PCIXReq64  
PCIXAck64  
PCIXReset  
Asserted by the current bus master, indicating a 64-bit transfer.  
Indicates the target can transfer data using 64 bits.  
I/O  
I/O  
O
3.3V PCI  
3.3V PCI  
3.3V PCI  
4
4
Brings PCI device registers and logic to a consistent state.  
Reports address parity errors, data parity errors on the Special  
Cycle command, or other catastrophic system errors.  
PCIXSErr  
PCIXStop  
PCIXTRDY  
I/O  
I/O  
I/O  
3.3V PCI  
3.3V PCI  
3.3V PCI  
4
4
4
Indicates the current target is requesting the master to stop the  
current transaction.  
Indicates the target agent’s ability to complete the current data  
phase of the transaction.  
48  
AMCC  
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